Reducing test data volume using external/LBIST hybrid test patterns

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 115-122

  Das, Debaleena ^a   Touba, Nur A ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS;

HYBRID TEST PATTERNS; TEST DATA VOLUME;

BUILT-IN SELF TEST;

EID: 0034478799     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)