Virtual scan chains: a means for reducing scan length in cores

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2000, Pages 73-78

  Jas, Abhijit ^a   Pouya, Bahram ^a   Touba, Nur A ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; CRITICAL PATH ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; INTELLECTUAL PROPERTY; MICROPROCESSOR CHIPS;

SYSTEM INTEGRATOR; TEST PATH GENERATION; VIRTUAL SCAN CHAINS;

DESIGN FOR TESTABILITY;

EID: 0033740888     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (11)