Hybrid BIST based on weighted pseudo-random testing: A new test resource partitioning scheme

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2001, Pages 2-8

  Jas, A ^a   Krishna, C V ^a   Touba, N A ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUILT-IN SELF TEST; COMPUTER ARCHITECTURE; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; RANDOM PROCESSES; VLSI CIRCUITS;

TEST RESOURCE PARTITIONING SCHEME; WEIGHTED PSEUDO RANDOM TESTING;

INTEGRATED CIRCUIT TESTING;

EID: 0035003537     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

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15. TESTCHIP: A chip for weighted random pattern generation, evaluation, and test control
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18. Multiple distributions for biased random test patterns