Test vector encoding using partial LFSR reseeding

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 885-893

  Krishna, C V ^a   Jas, Abhijit ^a   Touba, Nur A ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; ENCODING (SYMBOLS); POLYNOMIALS; TIMING CIRCUITS; VECTORS;

AUTOMATIC TEST EQUIPMENTS (ATE); CLOCK CYCLES;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035684018     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. Self-testing of multichip logic modules
2. Combinational profiles of sequential benchmark circuits
3. Linear dependencies in linear feedback shift registers
4. Generation of vector patterns through reseeding of multiple-polynomial linear feedback shift registers
5. Built-in test for circuits with scan based on reseeding of multiple-polynomial linear feedback shift registers
6. Pattern generation for a deterministic BIST scheme
7. Controllable LFSR for BIST
8. I/O bandwidth bottleneck for test: Is it real?
9. LFSR-coded test patterns for scan designs
10. Logic DFT and test resource partitioning for 100M gate ASICs
11. Test data decompression for multiple scan designs with boundary scan
12. An efficient BIST scheme based on reseeding of multiple polynomial linear feedback shift registers
13. Decompression of test data using variable-length seed LFSRs
14. Two dimensional test data decompressor for multiple scan designs