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Volumn 15, Issue 10, 1994, Pages 386-388

Ultrafast Operation of Vth-Adjusted P+ -n+ Double-Gate SOI MOSFET's

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC PROPERTIES; ELECTRODES; GATES (TRANSISTOR); OPTIMIZATION; OSCILLATORS (ELECTRONIC); SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY;

EID: 0028532218     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.320976     Document Type: Article
Times cited : (69)

References (10)
  • 1
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    • Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate
    • T. Sekigawa and Y. Hayashi, “Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate,” Solid-State Electron. vol. 827-828, pp. 1984.
    • (1984) Solid-State Electron , pp. 827-828
    • Sekigawa, T.1    Hayashi, Y.2
  • 2
    • 0023421993 scopus 로고
    • Double-gate silicon-on-insulator transistor with volume iriversion: A new device with greatly enhanced performance
    • F. Balestra, S. Christoloveanu, M. Benachir, and T. Elewa, “Double-gate silicon-on-insulator transistor with volume iriversion: A new device with greatly enhanced performance,” IEEE Electron Device Lett., vol. 8, pp. 410–412, 1987.
    • (1987) IEEE Electron Device Lett , vol.8 , pp. 410-412
    • Balestra, F.1    Christoloveanu, S.2    Benachir, M.3    Elewa, T.4
  • 4
    • 0025749775 scopus 로고    scopus 로고
    • Fabrication of double-gate thin-film SOI MOSFET's using wafer bonding and polishing
    • H. Horie, S. Ando, T. Tanaka, M. Imai, Y. Arimoto, and S. Hijiya, “Fabrication of double-gate thin-film SOI MOSFET's using wafer bonding and polishing,” 1991 SSDM Tech. Dig., pp. 165–167.
    • 1991 SSDM Tech. Dig. , pp. 165-167
    • Horie, H.1    Ando, S.2    Tanaka, T.3    Imai, M.4    Arimoto, Y.5    Hijiya, S.6
  • 5
    • 84954092771 scopus 로고
    • Analysis of p+ poly Si double-gate thin-film SOI MOSFET's
    • T. Tanaka, H. Horie, S. Ando, and S. Hijiya, “Analysis of p + poly Si double-gate thin-film SOI MOSFET's,” 1991 IEDM Tech. Dig., pp. 683–686.
    • (1991) IEDM Tech. Dig. , pp. 683-686
    • Tanaka, T.1    Horie, H.2    Ando, S.3    Hijiya, S.4
  • 6
    • 0026763758 scopus 로고
    • Dual-gate operation and volumeinversion in n-channel SOI MOSFET's
    • S. Venkatesan, G. W. Neudeck, and R. F. Pierret, “Dual-gate operation and volume inversion in n-channel SOI MOSFET's,” IEEE Electron Device Lett., vol. 13. no. 44–46, 1992.
    • (1992) IEEE Electron Device Lett. , vol.44–46
    • Venkatesan, S.1    Neudeck, G.W.2    Pierret, R.F.3
  • 7
    • 85056911965 scopus 로고    scopus 로고
    • Monte Carlo simulation of a 30 nm Dual-gate MOSFET: How short can Si go?
    • D. J. Frank. S. E. Laux, and M. V. Fischetti, “Monte Carlo simulation of a 30 nm Dual-gate MOSFET: How short can Si go?,” 1992 IEDM Tech. Dig., no. 553–556.
    • 1992 IEDM Tech. Dig., no , pp. 553-556
    • Frank, D.J.1    Laux, S.E.2    Fischetti, M.V.3
  • 9
    • 0028378433 scopus 로고
    • Analytical surface potential expression for thin-film double gate SOI MOSFET's
    • K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie Y. Arimoto, and T. Ito, “Analytical surface potential expression for thin-film double gate SOI MOSFET's,” Solid-State Electron., vol. 37, pp. 327–332, 1994.
    • (1994) Solid-State Electron. , vol.37 , pp. 327-332
    • Suzuki, K.1    Tanaka, T.2    Tosaka, Y.3    Horie, H.4    Arimoto, Y.5    Ito, T.6
  • 10
    • 0027889412 scopus 로고    scopus 로고
    • 21 psec switching 0.1µm-CMOS at room temperature using high performance Co salicide process
    • T. Yamazaki, K. Goto, T. Fukano, Y. Nara, T. Sugii, and T. Ito, “21 psec switching 0.1 µm-CMOS at room temperature using high performance Co salicide process,” 1993 IEDM Tech. Dig., pp. 906–908.
    • 1993 IEDM Tech. Dig. , pp. 906-908
    • Yamazaki, T.1    Goto, K.2    Fukano, T.3    Nara, Y.4    Sugii, T.5    Ito, T.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.