Threshold Voltage Model for Deep-Submicrometer MOSFET’s

IEEE Transactions on Electron Devices

Volumn 40, Issue 1, 1993, Pages 86-95

  Cheng, Y ^d   Hu, Chenming ^a   Huang, Jian Hui ^a   Ko, Ping K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b CYPRESS SEMICONDUCTOR   (United States)

^c CADENCE DESIGN SYSTEMS   (United States)

^d CITY UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

MATHEMATICAL MODELS; OXIDES; SEMICONDUCTOR JUNCTIONS; VOLTAGE MEASUREMENT;

CHANNEL DOPING; CHANNEL LENGTH; DEEP SUBMICROMETER MOSFETS; DRAIN VOLTAGE; GATE OXIDE THICKNESS EFECTS; LIGHTLY DOPED DRAIN (LDD) MOSFETS; NON-LDD MOSFETS; QUASI-TWO-DIMENSIONAL MODEL; SOURCE/DRAIN JUNCTION DEPTH; THRESHOLD VOLTAGE MODEL;

MOSFET DEVICES;

EID: 0027187367     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.249429     Document Type: Article

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