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Volumn 39, Issue 4, 1992, Pages 959-966

A High-Performance 0.25-μm CMOS Technology: I—Design and Characterization

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DEVICES--GATES; OSCILLATORS; SEMICONDUCTING SILICON; TRANSISTORS, FIELD EFFECT;

EID: 0026852069     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.127489     Document Type: Article
Times cited : (66)

References (17)
  • 3
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    • Design and characterization of the lightly doped drain-source (LDD) insulated gate field-effect transistor
    • S. Ogura, P. J. Tsang, W. W. Walker, D. L. Chritchlow, and J. F. Shepard, “Design and characterization of the lightly doped drain-source (LDD) insulated gate field-effect transistor,” IEEE Trans. Electron Devices, vol. ED-27, 1359, 1980.
    • (1980) IEEE Trans. Electron Devices , vol.ED-27 , pp. 1359
    • Ogura, S.1    Tsang, P.J.2    Walker, W.W.3    Chritchlow, D.L.4    Shepard, J.F.5
  • 6
    • 0003760989 scopus 로고    scopus 로고
    • SUPREM-II—A program for IC process modeling and simulation
    • Stanford University, Stanford, CA
    • D. A. Antoniadis, S. E. Hansen, and R. W. Dutton, “SUPREM-II—A program for IC process modeling and simulation,” Stanford Elec. Lab., Tech. Rep. 5019–2, Stanford University, Stanford, CA.
    • Stanford Elec. Lab., Tech. Rep , pp. 5019-5022
    • Antoniadis, D.A.1    Hansen, S.E.2    Dutton, R.W.3
  • 9
    • 0022751618 scopus 로고
    • Analysis of the gate-voltage-dependent series resistance of MOSFET's
    • K. K. Ng and W. T. Lynch, “Analysis of the gate-voltage-dependent series resistance of MOSFET's,” IEEE Trans. Electron Devices, vol. ED-33, p. 965, 1986.
    • (1986) IEEE Trans. Electron Devices , vol.ED-33 , pp. 965
    • Ng, K.K.1    Lynch, W.T.2
  • 10
    • 0022027064 scopus 로고
    • Design tradeoffs between surface and buried-channel FET's
    • G. J. Hu and R. H. Bruce, “Design tradeoffs between surface and buried-channel FET's,” IEEE Trans. Electron Devices, vol. ED-32, 584, 1985.
    • (1985) IEEE Trans. Electron Devices , vol.ED-32 , pp. 584
    • Hu, G.J.1    Bruce, R.H.2
  • 11
    • 0023604110 scopus 로고
    • Design methodology for deep submicron CMOS
    • K. Tanaka and M. Fukuma, “Design methodology for deep submicron CMOS,” in IEDM Tech. Dig., 1987, p. 628.
    • (1987) IEDM Tech. Dig , pp. 628
    • Tanaka, K.1    Fukuma, M.2
  • 12
    • 0023590852 scopus 로고
    • Submicron tungsten gate mosfet's with 10 nm gate oxide
    • B. Davari et al., “Submicron tungsten gate mosfet's with 10 nm gate oxide,” in 1987 Symp. VLSI Tech. Dig., p. 61.
    • (1987) Symp. VLSI Tech. Dig , pp. 61
    • Davari, B.1
  • 14
    • 0018468995 scopus 로고
    • A new method to determine effective MOSFET channel length
    • K. Terada, and H. Muta, “A new method to determine effective MOSFET channel length,” Japan. J. Appl. Phys., vol. 18, p. 953, 1979.
    • (1979) Japan. J. Appl. Phys , vol.18 , pp. 953
    • Terada, K.1    Muta, H.2
  • 15
    • 0024143472 scopus 로고
    • Measurement of threshold voltages and channel length of submicron MOSFETs
    • S. Jain, “Measurement of threshold voltages and channel length of submicron MOSFETs,” Proc. Inst. Elec. Eng., vol. 135, pt. I, p. 162, 1988.
    • (1988) Proc. Inst. Elec. Eng , vol.135 , pp. 162
    • Jain, S.1
  • 17
    • 0020797242 scopus 로고
    • Effects of hot-carrier trapping in n-and p-channel MOSFET's
    • K. K. Ng and G. W. Taylor, “Effects of hot-carrier trapping in n-and p-channel MOSFET's,” IEEE Trans. Electron Devices, vol. ED-30, p. 871, 1983.
    • (1983) IEEE Trans. Electron Devices , vol.ED-30 , pp. 871
    • Ng, K.K.1    Taylor, G.W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.