-
1
-
-
0003344263
-
The submicrometer silicon MOSFET
-
R. K. Watts, Ed. New York Wiley ch. 1.
-
J. R. Brews, K. K. Ng, and R. K, Watts, “The submicrometer silicon MOSFET,” in Submicron Integrated Circuits, R. K. Watts, Ed. New York: Wiley, 1989, ch. 1.
-
(1989)
Submicron Integrated Circuits
-
-
Brews, J.R.1
Ng, K.K.2
Watts, R.K.3
-
2
-
-
0039956433
-
Generalized guide for MOSFET miniaturization
-
J.R., Brews, W. Fichtner, E. H. Nicollian, and S. M. Sze, “Generalized guide for MOSFET miniaturization/’ IEEE Electron Device Lett., vol. EDL-1, p. 2, 1980.
-
(1980)
IEEE Electron Device Lett.
, vol.EDL-1
, pp. 2
-
-
Brews, J.R.1
Fichtner, W.2
Nicollian, E.H.3
Sze, S.M.4
-
3
-
-
0024612456
-
Short-channel effect in fully-depleted SOI MOSFET’s
-
K. K. Young, “Short-channel effect in fully-depleted SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 36, 339, 1989.
-
(1989)
IEEE Trans. Electron Devices
, vol.36
, Issue.339
-
-
Young, K.K.1
-
4
-
-
84942394757
-
-
PADRE 2.1, AT&T Bell Laboratories
-
M. R. Pinto and R. K. Smith, PADRE 2.1, AT&T Bell Laboratories.
-
-
-
Pinto, M.R.1
Smith, R.K.2
-
5
-
-
0026817615
-
A semi-empirical model of surface scattering for Monte Carlo simulation of silicon n-MOSFET’s
-
Feb.
-
E. Sangiorgi and M. R. Pinto, “A semi-empirical model of surface scattering for Monte Carlo simulation of silicon n-MOSFET‘s,” IEEE Trans. Electron Devices, vol. 39. no. 2. pp. 356–361, Feb. 1992.
-
(1992)
IEEE Trans. Electron Devices
, vol.39.
, Issue.2
, pp. 356-361
-
-
Sangiorgi, E.1
Pinto, M.R.2
-
6
-
-
0021406605
-
Generalized scaling theory and its application to a 1/4 micrometer MOSFET design
-
G. Baccarani, M. R. Wordeman, and R. H. Dennard. “Generalized scaling theory and its application to a 1/4 micrometer MOSFET design,’ IEEE Trans. Electron Devices, vol. ED-31, 452, 1984.
-
(1984)
IEEE Trans. Electron Devices
, vol.ED-31
, Issue.452
-
-
Baccarani, G.1
Wordeman, M.R.2
Dennard, R.H.3
-
7
-
-
0016116644
-
Design of ion-implanted MOSFET’s with very small physical dimensions
-
R. H. Dennard, F. H. Gaensslen, H.-N. Yu, V. L. Rideout, E. Bas-sous, and A. R. LeBlanc, “Design of ion-implanted MOSFET’s with very small physical dimensions,” IEEE J. Solid-State Circuits, vol. SC-9, p. 256, 1974.
-
(1974)
IEEE J. Solid-State Circuits
, vol.SC-9
, pp. 256
-
-
Dennard, R.H.1
Gaensslen, F.H.2
Yu, H.N.3
Rideout, V.L.4
Bas-sous, E.5
LeBlanc, A.R.6
-
8
-
-
0009599273
-
Characterization of the electron mobility in the inverted < 100> Si surface
-
A. G. Sabnis and J. T. Clemens, “Characterization of the electron mobility in the inverted < 100> Si surface,” in IEDM Tech. Deg., 1979, p. 18.
-
(1979)
IEDM Tech. Deg.
, pp. 18
-
-
Sabnis, A.G.1
Clemens, J.T.2
-
9
-
-
84941448723
-
Design and experimental technology for 0.1 μm gate-length low-temperature operation FET’s
-
M. R. Polcari. H. Y. Ng, P. J. Restle, T. H. P. Chang, and R. H. Dennard
-
G. A. Sai-Halasz, M. R. Wordeman, D. P. Kern, E. Ganin, S. Rishton, D. S. Zicherman, H. Schmid. M. R. Polcari. H. Y. Ng, P. J. Restle, T. H. P. Chang, and R. H. Dennard, “Design and experimental technology for 0.1 μm gate-length low-temperature operation FET’s,” IEEE Electron Device Lett., vol. EDL-8, 463, 1987.
-
(1987)
IEEE Electron Device Lett.
, vol.EDL-8
, Issue.463
-
-
Sai-Halasz, G.A.1
Wordeman, M.R.2
Kern, D.P.3
Ganin, E.4
Rishton, S.5
Zicherman, D.S.6
Schmid, H.7
-
10
-
-
0022663346
-
Reduction of floating substrate effect in thin-film SOI MOSFET’s
-
J.P. Colinge, “Reduction of floating substrate effect in thin-film SOI MOSFET’s,” Electron Lett., vol. 22, p. 187, 1986.
-
(1986)
Electron Lett.
, vol.22
, pp. 187
-
-
Colinge, J.P.1
-
11
-
-
0024647355
-
Analysis study of punchthrough in buried channel p-MOSFET’s
-
T. Shotnicki. G. Merckel, and T. Pedron, “Analysis study of punchthrough in buried channel p-MOSFET’s,” IEEE Trans. Electron Devices, vol. 36, p. 690, 1989.
-
(1989)
IEEE Trans. Electron Devices
, vol.36
, pp. 690
-
-
Shotnicki, T.1
Merckel, G.2
Pedron, T.3
-
12
-
-
0025486394
-
Two-dimensional analysis modeling of very thin SOI MOSFET’s
-
J. C. S. Woo, K. W. Terrill, and P. K. Vasudev, “Two-dimensional analysis modeling of very thin SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 37, p. 1999, 1990.
-
(1990)
IEEE Trans. Electron Devices
, vol.37
, pp. 1999
-
-
Woo, J.C.S.1
Terrill, K.W.2
Vasudev, P.K.3
-
13
-
-
0024626928
-
Analysis of conduction in fully depleted SOI MOSFET’s
-
K K. Young, “Analysis of conduction in fully depleted SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 36, p. 504, 1989.
-
(1989)
IEEE Trans. Electron Devices
, vol.36
, pp. 504
-
-
Young, K.K.1
-
14
-
-
6344290643
-
Calculateh threshold-voltage characteristics of an XMOS transistor having an additional bottom gate
-
T. Kekigawa and Y. Hayashi, “Calculateh threshold-voltage characteristics of an XMOS transistor having an additional bottom gate,” Solid-State Electron., vol. 27, p. 827, 1984.
-
(1984)
Solid-State Electron.
, vol.27
, pp. 827
-
-
Kekigawa, T.1
Hayashi, Y.2
-
15
-
-
0025575976
-
Silicon-on-insulator gate-all-around devices
-
J.-P. Colinge, M. H. Gao, A. Romano-Rodriguez, H. Maes, and C. Claeys, “Silicon-on-insulator gate-all-around devices,” in IEDM Tech. Dig., 1990, p. 595.
-
(1990)
IEDM Tech. Dig.
, pp. 595
-
-
Colinge, J.P.1
Gao, M.H.2
Romano-Rodriguez, A.3
Maes, H.4
Claeys, C.5
-
16
-
-
0022893930
-
Trends in advanced CMOS process technology
-
D. M. Brown, M. Ghezzo, and J. M. Pimbley, “Trends in advanced CMOS process technology,” Proc. IEEE, vol. 74, p. 1678, 1986.
-
(1986)
Proc. IEEE
, vol.74
, pp. 1678
-
-
Brown, D.M.1
Ghezzo, M.2
Pimbley, J.M.3
-
17
-
-
84942393055
-
CMOS active and field device fabrication
-
L. C. Parrillo, “CMOS active and field device fabrication,” Semicond. Internat., p. 64, 1988.
-
(1988)
Semicond. Internat.
, pp. 64
-
-
Parrillo, L.C.1
-
18
-
-
0025578245
-
0.1 μm CMOS devices using low-impurity-channel transistors (LICT)
-
M. Aoki, T. I.shii, T. Yoshimura, Y. Kiyota, S. Iijima, T. Yamanaka, T. Kure. K. Ohyu, T. Hishida, S. Okazaki, K. Seki, and K. Shimohihashi, “0.1 μm CMOS devices using low-impurity-channel transistors (LICT),” in IEDM Tech. Dig., 1990, p. 939.
-
(1990)
IEDM Tech. Dig.
, pp. 939
-
-
Aoki, M.1
Shii, T.I.2
Yoshimura, T.3
Kiyota, Y.4
Iijima, S.5
Yamanaka, T.6
Kure, T.7
Ohyu, K.8
Hishida, T.9
Okazaki, S.10
Seki, K.11
Shimohihashi, K.12
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