Scaling the MOS Transistor Below 0.1 µm: Methodology, Device Structures, and Technology Requirements

IEEE Transactions on Electron Devices

Volumn 41, Issue 6, 1994, Pages 941-951

  Fiegna, Claudio ^a   Iwai, Hiroshi ^b   Wada, Tetsunori ^b   Saito, Masanobu ^b   Sangiorgi, Enrico ^c   Riccò, Bruno ^d  

^a UNIVERSITY OF FERRARA   (Italy)

^b TOSHIBA CORPORATION   (Japan)

^c UNIVERSITY OF UDINE   (Italy)

^d UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; COMMUNICATION CHANNELS (INFORMATION THEORY); GATES (TRANSISTOR); SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; ULSI CIRCUITS; VOLTAGE MEASUREMENT;

CHANNEL LENGTHS; OXIDE THICKNESS; SUPPLY VOLTAGE;

MOSFET DEVICES;

EID: 0028448562     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.293306     Document Type: Article

References (31)

1. M. Aoki, T. Ishii, T. Yoshimura, Y. Kiyota, S. Iijima, T. Yamanaka, T. Kure, K. Ohyu, T. Nishida, S. Okazaki, K. Seki, and K. Shimohigashi, “0.1 µm CMOS devices using low-impurity-channel transistors (LICT),” in IEDM Tech. Dig., pp. 939-941, 1990.
2. D. A. Antoniadis and J. E. Chung, “Physics and technology of ultra-short channel MOSFET devices,” in IEDM Tech. Dig., pp. 21-24, 1991.
3. R. H. Yan, A. Ourmazd, K. F. Lee, D. Y. Leon, C. S. Rafferty, and M. R. Pinto, “Scaling the silico-oxide-semiconductor field-effect transistor into the 0.1 pm regime using vertical doping engineering,” Appl. Phys. Lett., Vol. 59, pp. 3315-3317, 1991.
4. T. Hashimoto, Y. Sudoh, H. Kurino, A. Narai, S. Yokoyama, Y. Horiike, and M. Koyanagi, “3 V operation of 70 nm gate length MOSFET with new double punchthrough stopper structure,” Ext. Abs. of Int. Conf. on Solid State Devices and Materials, pp. 490-492, 1992.
5. D. J. Frank, S. E Laux and M. V. Fischetti, “Monte Carlo simulation of a 30 nm dual-gate MOSFET: how short can Si go?,” in IEDM Tech. Dig., pp. 553-556, 1992.
6. A. Toriumi, T. Mizuno, M. Iwase, M. Takahashi, H. Niiyama, M. Fukumoto, S. Inaba, I. Mori, and M. Yoshimi, “High speed 0.1 pm CMOS devices operating at room temperature,” in Ext. Abs. of Int. Conf on Solid State Devices and Materials, pp. 487-489, 1992.
7. M. Saito, T. Yoshitomi, M. Ono, Y. Akasaka, H. Nii, S. Matsuda, H. Momose, Y. Katsumata, Y. Ushiku, and H. Iwai, “An SPDD MOSFET structure suitable for 0.1 pm and sub 0.1 µm channel length and its electrical characterization,” IEDM Tech. Dig., pp. 897-900, 1992.
8. T. Morimoto, H. S. Momose, M. Tsuchiaki, Y. Ozawa, K. Yamabe, and H. Iwai, “Limits on gate insulator thickness for MISFET operation in pure-oxide and nitride-oxide gate cases,” Ext. Abs. of Int. Conf. on Solid State Devices and Materials, pp. 23-25, 1991.
9. J. R. Brews, High speed Semiconductor Devices, S. M. Sze, Ed. New York: Wiley Interscience, 1990.
10. F. Stem and W. E. Howard, “Properties of semiconductor surface inversion layers in the electric quantum limit,” Phys. Rev., Vol. 163, No. 3, pp. 816-835, 1967
11. H. Ohkura, “Quantum effects in Si n-MOS inversion layer at high substrate concentration,” Solid State Electron., vol. 33, no. 12, pp. 1581-1585, 1990.
12. T. Yoshitomi, M. Saito, H. Oguma, Y. Akasaka, M. Ono, H. Nii, Y. Ushiku, H. Iwai, and H. Hara, “Ultra-shallow buried-channel p-MOSFET with extremely high transconductance,” 1993 Symp. on VLSI Technol. Tech. Dig.
13. K. Nishinohara, N. Shigyo, and Tetsunori Wada, “Effects of microscopic fluctuations in doping distributions on MOSFET threshold voltage,” IEEE Trans. Electron Devices, vol. 39, pp. 634-639, 1992.
14. Colinge, Silicon on Insulator Technology: Materials to VLSI. New York: Kluwer, 1990.
15. J. G. Fossum, S. Krishnan, and P.-C. Yeh, “Performance limitations of deep-submicron fully depleted SOI MOSFET’s" 1992 IEEE Int. SOI Conf. Proc., pp. 132-133.
16. Y. Omura, S. Nakashima, K. Izumi, and T. Ishii, “0.1 µm-gate, ultrathin-film CMOS devices using SIMOX substrate with 80 nm-thick buried oxide layer,” IEDM Tech. Dig., pp. 675-678, 1992.
17. M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, “Sub-50 nm gate length n-MOSFET’s with 10 nm phosphorous source and drain junctions,” IEDM Tech. Dig., pp. 119-122, 1993.
18. F. Venturi, E. Sangiorgi, and B. Riccó, “The impact of voltage scaling on electron heating and device performance of submicrometer MOSFET’s,” IEEE Trans. Electron Devices, vol. 38, pp. 1895-1904, 1991.
19. K. Yano, D. K. Ferry, and K. Seki, “Molecular-dynamics study of charge quantization on 1-100 nm Si-MOSFET,” IEDM Tech. Dig., pp. 557-560, 1992.
20. D. K. Ferry, A. M. Kriman, M. J. Kann, and R. P. J. Joshi, Computer Physics Commun., vol. 67, p. 119, 1991.
21. J. R. Barker and D. K. Ferry, “On the physics and modeling of small semiconductor devices—I,” Solid State Electron., vol. 23, pp. 519-130, 1980.
22. S. K. Sarker, J. H. Davies, F. S. Kahn, and J. W. Wilkins, “Quantum corrections to the Boltzmann equation for transport in semiconductors in high electric fields,” Phys. Rev. B, vol. 33, pp. 7263-7266, 1986.
23. T. Wada and R. Dang, “Development and application of a high-speed 2-dimensional; time dependent device simulator (MOS2C),” Proc. NASECODE IV, p. 108, 1985.
24. R. Brunetti, C. Jacoboni, F. Venturi, E. Sangiorgi, and B. Riccò, “A many-band silicon model for hot-electron transport at high energies,” Solid State Electron., vol. 32, 1663-1667, 1989.
25. C. Fiegna and E. Sangiorgi, “Modeling of high energy electrons in silicon at the microscopic level,” IEEE Trans. Electron Devices, vol. 40, pp. 619-627, 1993.
26. F. Venturi, A. Abramo, E. Sangiorgi, J. Higman, C. Fiegna, and B. Ricco, “An isotropic best-fitting band model for electrons and hole transport in Silicon,” IEDM Tech. Dig., pp. 503-506, 1991.
27. J. T. Watt and J. D. Plummer, “Universal mobility-field curves for electrons and holes in MOSFET inversion layers,” 1981 Symp. on VLSI Technol. Tech. Dig., pp. 81-82, 1981.
28. G. G. Shahidi, D. A. Antoniadis, and H. I. Smith. “Reduction of channel hot-electron-generated substrate current in sub 150 nm channel length Si MOSFET’s,” IEEE Electron Dev. Lett., vol. 9, pp. 497-499, 1988.
29. T. Mizuno, A. Toriumi, M. Iwase, M. Takahashi, H. Niiyama, M. Fukumoto, and M. Yoshimi, “Hot carrier effects in 0.1 pm gate length CMOS devices,” in IEDM Tech. Dig, pp. 695-698, 1992.
30. L. Manchanda, R. H. Storz, R. H. Yan, K. F. Lee, and E. H. Westerwick, “Clear observation of sub-band gap impact ionization at room temperature and below in 0.1 pm Si MOSFETs,” IEDM Tech. Dig., pp. 994-996, 1992.
31. H. Takemura, “BSA technology for sub-100 nm deep base bipolar transistors,” in IEDM Tech. Dig., pp. 375-378, 1987.