-
1
-
-
0003733185
-
Hardware/Software Co-Design: Principles and Practice
-
Kluwer Academic Publishers, Boston
-
Jorgen Stunstrup and Wayne Wolf, Hardware/Software Co-Design: Principles and Practice, Kluwer Academic Publishers, Boston, 1997.
-
(1997)
-
-
Stunstrup, J.1
Wolf, W.2
-
2
-
-
0003840779
-
Surviving the SOC Revolution, p. 71
-
Kluwer Academic Publishers, Boston
-
Henry Chang, Larry Cooke, Merrill Hunt, Grant Martin, Andrew McNelly, Lee Todd, Surviving the SOC Revolution, p. 71, Kluwer Academic Publishers, Boston, 1999.
-
(1999)
-
-
Chang, H.1
Cooke, L.2
Hunt, M.3
Martin, G.4
McNelly, A.5
Todd, L.6
-
3
-
-
85128672637
-
System LSI Design Engineering
-
Ohmsha, Tokyo
-
M. Fujita, System LSI Design Engineering, Ohmsha, Tokyo, 2006.
-
(2006)
-
-
Fujita, M.1
-
4
-
-
0003903283
-
SYSTEM DESIGN, A Practical Guide with SpecC
-
Kluwer Academic Publishers, Boston
-
A. Gerstlauer, et al, SYSTEM DESIGN, A Practical Guide with SpecC, Kluwer Academic Publishers, Boston, 2001.
-
(2001)
-
-
Gerstlauer, A.1
-
5
-
-
3042681847
-
Winning the SoC Revolution
-
Kluwer Academic Publishers, Boston
-
Grant Martin and Henry Chang, Winning the SoC Revolution, Kluwer Academic Publishers, Boston, 2003.
-
(2003)
-
-
Martin, G.1
Chang, H.2
-
7
-
-
85128622248
-
"Introducing PS2 to PC programmers,"
-
Australian Game Developers Conference, December
-
David Carter, "Introducing PS2 to PC programmers," Australian Game Developers Conference, December 2002.
-
(2002)
-
-
Carter, D.1
-
8
-
-
84882915723
-
Multiprocessor Systems-on-Chips
-
Morgan Kaufmann Publishers, San Francisco
-
Ahmed A. Jerraya and Wayne Wolf, Multiprocessor Systems-on-Chips, Morgan Kaufmann Publishers, San Francisco, 2005.
-
(2005)
-
-
Jerraya, A.A.1
Wolf, W.2
-
9
-
-
0003662159
-
Parallel Computer Architecture
-
Morgan Kaufmann Publishers, San Francisco
-
David E. Culler and Jaswinder P. Singh, Parallel Computer Architecture, Morgan Kaufmann Publishers, San Francisco, 1999.
-
(1999)
-
-
Culler, D.E.1
Singh, J.P.2
-
10
-
-
0003397196
-
Low Power Digital CMOS Design
-
Kluwer Academic Publishers, Boston
-
A.P. Chndrakasan and R.W. Broderson, Low Power Digital CMOS Design, Kluwer Academic Publishers, Boston, 1996.
-
(1996)
-
-
Chndrakasan, A.P.1
Broderson, R.W.2
-
11
-
-
0004173639
-
Low Power Design Methodologies
-
Kluwer Academic Publishers, Boston
-
J.M. Rabaey and M. Pedram, Low Power Design Methodologies, Kluwer Academic Publishers, Boston, 1996.
-
(1996)
-
-
Rabaey, J.M.1
Pedram, M.2
-
12
-
-
84886220414
-
Low Power CMOS Design
-
Asia and South Pacific Design Automation Conference 2007 Tutorials.
-
A. Gupta and T. Hattori, Low Power CMOS Design, Asia and South Pacific Design Automation Conference 2007 Tutorials.
-
-
-
Gupta, A.1
Hattori, T.2
-
13
-
-
0003844699
-
UML Distilled
-
3rd ed, Addison-Wesley.
-
Martin Fowler, UML Distilled, 3rd ed, Addison-Wesley.
-
-
-
Fowler, M.1
-
14
-
-
0003652206
-
SpecC: Specification Language and Methodology
-
Kluwer Academic Publisher, Boston, March
-
Daniel D. Gajski, Zhu, J., Rainer Doemer, Gerstlauer, A., Zhao, S., SpecC: Specification Language and Methodology, Kluwer Academic Publisher, Boston, March 2000.
-
(2000)
-
-
Gajski, D.D.1
Zhu, J.2
Doemer, R.3
Gerstlauer, A.4
Zhao, S.5
-
15
-
-
19344374153
-
Modeling Embedded Systems and SoCs: Concurrency and Time in Models of Computation
-
Morgan Kaufmann Publisher.
-
Axel Jantsch, Modeling Embedded Systems and SoCs: Concurrency and Time in Models of Computation, Morgan Kaufmann Publisher.
-
-
-
Jantsch, A.1
-
16
-
-
0003669295
-
Theory of Modeling and Simulation
-
Academic Press
-
Bernard P. Zeigler, Tag Gon Kim, and Herbert Praehofer, Theory of Modeling and Simulation, Academic Press, 2000.
-
(2000)
-
-
Zeigler, B.P.1
Kim, T.G.2
Praehofer, H.3
-
17
-
-
0003558118
-
High Level Synthesis: Introduction to Chip and System Design
-
Kluwer Academic Publishers.
-
D. Gajski et al., High Level Synthesis: Introduction to Chip and System Design, Kluwer Academic Publishers.
-
-
-
Gajski, D.1
-
19
-
-
5244346247
-
Dataflow Computation
-
CWI Tracts
-
A.P.W. Bohm, Dataflow Computation, CWI Tracts, 1983.
-
(1983)
-
-
Bohm, A.P.W.1
-
20
-
-
85128698189
-
A Formal Definition of Data Flow Graph Models
-
IEEE Transactions of Computer, November
-
Kavi K.M., et al., A Formal Definition of Data Flow Graph Models, IEEE Transactions of Computer, November 1986.
-
(1986)
-
-
Kavi, K.M.1
-
21
-
-
0029309183
-
Dataflow Process Networks
-
Edward A. Lee and Thomas M. Parks, Dataflow Process Networks, Proc. IEEE, Vol. 83, no. 5, pp. 773-801, 1995.
-
(1995)
Proc. IEEE
, vol.83
, Issue.5
, pp. 773-801
-
-
Lee, E.A.1
Parks, T.M.2
-
22
-
-
0003983220
-
Software Synthesis from Dataflow Graphs
-
Kluwer Academic Press
-
S.S. Bhattacharyya et al., Software Synthesis from Dataflow Graphs, Kluwer Academic Press, 1996.
-
(1996)
-
-
Bhattacharyya, S.S.1
-
23
-
-
0000087207
-
The Semantics of a Simple Language for Parallel Programming
-
Rosenfeld, J.L., Ed., North-Holland, Amsterdam
-
Gilles Kahn, The Semantics of a Simple Language for Parallel Programming, in Proc. IFIP 74, Rosenfeld, J.L., Ed., North-Holland, Amsterdam, 1974, pp. 471-475.
-
(1974)
in Proc. IFIP 74
, pp. 471-475
-
-
Kahn, G.1
-
25
-
-
0003558118
-
High-level Synthesis: Introduction to Chip and System Design
-
Springer.
-
Daniel D. Gajski et al., High-level Synthesis: Introduction to Chip and System Design, Springer.
-
-
-
Gajski, D.D.1
-
26
-
-
0004189966
-
Algebraic Theory of Processes
-
The MIT Press.
-
Matthew Hennessy, Algebraic Theory of Processes The MIT Press.
-
-
-
Hennessy, M.1
-
27
-
-
0003954103
-
Communication and Concurrency
-
Prentice Hall
-
Robin Milner, Communication and Concurrency, Prentice Hall, 1989.
-
(1989)
-
-
Milner, R.1
-
28
-
-
0018005391
-
Communicating Sequential Processes
-
Hoare, C. A. R., Communicating Sequential Processes, Communications of the ACM, 21(8), pp. 666-676, 1978.
-
(1978)
Communications of the ACM
, vol.21
, Issue.8
, pp. 666-676
-
-
Hoare, C.A.R.1
-
29
-
-
0003464858
-
The formal description technique LOTOS
-
Elsevier Science Publishers B.V.
-
Van Eijk, P. H. J., Vissers, C. A., Diaz, M., The formal description technique LOTOS, Elsevier Science Publishers B.V., 1989.
-
(1989)
-
-
Van Eijk, P.H.J.1
Vissers, C.A.2
Diaz, M.3
-
30
-
-
33846327313
-
A Comparative Introduction to CSP, CCS and LOTOS
-
Technical Paper No.93-24, Software Verification Research Center, Dept. of CS, University of Queensland
-
Colin Fidge, A Comparative Introduction to CSP, CCS and LOTOS, Technical Paper No.93-24, Software Verification Research Center, Dept. of CS, University of Queensland, 1994.
-
(1994)
-
-
Fidge, C.1
-
31
-
-
84882915723
-
Multiprocessor Systems-on-Chips
-
Morgan Kaufmann Publishers, San Francisco
-
Ahmed A. Jerraya and Wayne Wolf, Multiprocessor Systems-on-Chips, Morgan Kaufmann Publishers, San Francisco, 2005.
-
(2005)
-
-
Jerraya, A.A.1
Wolf, W.2
-
32
-
-
0004209425
-
Principles of Digital Design
-
Prentice Hall, Upper Saddle River, NJ
-
Daniel D. Gajski, Principles of Digital Design, Prentice Hall, Upper Saddle River, NJ, 1997.
-
(1997)
-
-
Gajski, D.D.1
-
33
-
-
0242661955
-
Formal Methods in Embedded Design, Computer
-
November
-
Steven D. Johnson, Formal Methods in Embedded Design, Computer, pp. 104-106, November 2003.
-
(2003)
, pp. 104-106
-
-
Johnson, S.D.1
-
34
-
-
34347218500
-
Platform-based Design: A Choice, not a Panacea
-
November 09
-
Richard Goering, Platform-based Design: A Choice, not a Panacea, EE times, November 09, 2002.
-
(2002)
EE times
-
-
Goering, R.1
-
37
-
-
85128657341
-
Platform-Based Design: An Emerging Reality
-
SoC Online, October
-
Bob Altizer, Platform-Based Design: An Emerging Reality, SoC Online, October 2003.
-
(2003)
-
-
Altizer, B.1
-
38
-
-
55849129666
-
Flexible Platform-Based Design
-
February
-
Jean-Marc Chateau, Flexible Platform-Based Design, EE Design, February 2001.
-
(2001)
EE Design
-
-
Chateau, J.-M.1
-
39
-
-
34548851961
-
One-dimensional Search Algorithms for Hardware/Software Partitioning
-
June
-
Wu Jigang, Thambipillai Srikanthan, and Guang Chen, One-dimensional Search Algorithms for Hardware/Software Partitioning, 5th IEEE/ACM Int. Conf. on Formal Methods and Models for Codesign, pp. 149-158, June 2007.
-
(2007)
5th IEEE/ACM Int. Conf. on Formal Methods and Models for Codesign
, pp. 149-158
-
-
Jigang, W.1
Srikanthan, T.2
Chen, G.3
-
40
-
-
0030784055
-
System Level Hard- ware/Software Partitioning Based on Simulated Annealing and Tabu Search
-
January
-
Petru Eles, Zebo Peng, Krzysztof Kuchcinski, and Alexa Doboli, System Level Hard- ware/Software Partitioning Based on Simulated Annealing and Tabu Search, Kluwer J. Design Automation for Embedded Systems, Vol. 2, No. 1, pp. 5-32, January 1997.
-
(1997)
Kluwer J. Design Automation for Embedded Systems
, vol.2
, Issue.1
, pp. 5-32
-
-
Eles, P.1
Peng, Z.2
Kuchcinski, K.3
Doboli, A.4
-
41
-
-
0001858873
-
Hardware-Software Cosynthesis for Digital Systems
-
Rajesh Gupta and Giovanni De Michelli, Hardware-Software Cosynthesis for Digital Systems, IEEE Design and Test of Computers, Vol. 10, No. 3, pp. 29-41, 1993.
-
(1993)
IEEE Design and Test of Computers
, vol.10
, Issue.3
, pp. 29-41
-
-
Gupta, R.1
Michelli, G.D.2
-
42
-
-
0028714173
-
A Binary-Constraint Search Algorithm for Minimizing Hardware during Hardware/Software Partitioning
-
September
-
Frank Vahid, Jie Gong, and Daniel D. Gajki, A Binary-Constraint Search Algorithm for Minimizing Hardware during Hardware/Software Partitioning, European Design Automation Conf., pp. 214-219, September 1994.
-
(1994)
European Design Automation Conf.
, pp. 214-219
-
-
Vahid, F.1
Gong, J.2
Gajki, D.D.3
-
43
-
-
0030684242
-
Functional Partitioning for Hardware-Software Codesign using Genetic Algorithms
-
Hidalgo, J., Lanchares, J., Functional Partitioning for Hardware-Software Codesign using Genetic Algorithms, 23rd EUROMICRO Conf., pp. 631-638, 1997.
-
(1997)
23rd EUROMICRO Conf.
, pp. 631-638
-
-
Hidalgo, J.1
Lanchares, J.2
-
44
-
-
33847146695
-
A Hybrid Genetic Algorithm for Constrained Hardware-Software Partitioning
-
April
-
Pierre-Andre Mudry, Guillaume Zufferey, and Gianluca Tempesti, A Hybrid Genetic Algorithm for Constrained Hardware-Software Partitioning, Design and Diagnostics of Electronic Circuits and Systems, pp. 1-6, April 2006.
-
(2006)
Design and Diagnostics of Electronic Circuits and Systems
, pp. 1-6
-
-
Mudry, P.-A.1
Zufferey, G.2
Tempesti, G.3
-
45
-
-
0031099473
-
Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning
-
Frank Vahid and Thuy Dm Le, Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning, Design Automation for Embedded Systems, 2, pp. 237-261, 1997.
-
(1997)
Design Automation for Embedded Systems
, vol.2
, pp. 237-261
-
-
Vahid, F.1
Le, T.D.2
-
46
-
-
31044445128
-
A Survey of Behavioral-level Partitioning Systems
-
UC Irvine, Technical Report, #91-71, October 30
-
Frank Vahid, A Survey of Behavioral-level Partitioning Systems, UC Irvine, Technical Report, #91-71, October 30, 1991.
-
(1991)
-
-
Vahid, F.1
-
47
-
-
22444453296
-
Functional Partitioning Improvements over Structural Partitioning for Packaging Constraints and Synthesis: Tool Performance
-
Frank Vahid, Thuy Dm Le, and Yu-Chin Hsu, Functional Partitioning Improvements over Structural Partitioning for Packaging Constraints and Synthesis: Tool Performance, ACM Transactions on Design Automation of Electronic Systems, Vol. 3, issue 2, pp. 181-208, 1998.
-
(1998)
ACM Transactions on Design Automation of Electronic Systems
, vol.3
, Issue.2
, pp. 181-208
-
-
Vahid, F.1
Le, T.D.2
Hsu, Y.-C.3
-
48
-
-
0026186345
-
Architectural Partitioning for System Level Synthesis of Integrated Circuits
-
July
-
Elizabeth Dirkes Lagnese and Donald E. Thomas, Architectural Partitioning for System Level Synthesis of Integrated Circuits, IEEE Transactions on Computer-Aided Design, Vol. 10, No.7, July 1991.
-
(1991)
IEEE Transactions on Computer-Aided Design
, vol.10
, Issue.7
-
-
Lagnese, E.D.1
Thomas, D.E.2
-
49
-
-
0030420178
-
A Comparison of Functional and Structural Partitioning
-
La Jolla
-
Frank Vahid, Thuy Dm Le, and Yu-Chin Hsu, A Comparison of Functional and Structural Partitioning, Int. Symp. on System Synthesis, pp. 121-126, La Jolla, 1996.
-
(1996)
Int. Symp. on System Synthesis
, pp. 121-126
-
-
Vahid, F.1
Le, T.D.2
Hsu, Y.-C.3
-
50
-
-
0001627504
-
Complexity Results for Multiprocessor Scheduling under Resource Constraints
-
Garey, M.R., Johnson, D.S. Complexity Results for Multiprocessor Scheduling under Resource Constraints, SIAM J. Computing, Vol. 4, Issue 4, 1975.
-
(1975)
SIAM J. Computing
, vol.4
, Issue.4
-
-
Garey, M.R.1
Johnson, D.S.2
-
51
-
-
33644607017
-
Time-Constrained Scheduling of Large Pipelined Data Paths
-
Peter Arato et al., Time-Constrained Scheduling of Large Pipelined Data Paths, J. System Architecture, 51, 2005, pp. 665-687.
-
(2005)
J. System Architecture
, vol.51
, pp. 665-687
-
-
Arato, P.1
-
52
-
-
0029483211
-
High-level Synthesis Scheduling and Allocation using Genetic Algorithm
-
Heijligers, M.J.M., et al., High-level Synthesis Scheduling and Allocation using Genetic Algorithm, Proc. Asia South Pacific Design Automation Conf., 1995, pp. 61-66.
-
(1995)
Proc. Asia South Pacific Design Automation Conf.
, pp. 61-66
-
-
Heijligers, M.J.M.1
-
54
-
-
85128589994
-
Bus Protocols Limit Design Reuse of IP
-
May 15
-
Ed Smith, Bus Protocols Limit Design Reuse of IP, EE Times, May 15, 2000.
-
(2000)
EE Times
-
-
Smith, E.1
-
56
-
-
85128642904
-
SpecC Methodology for High-level Modeling
-
IEEE/DATC Electronic Design Processes Workshop
-
Rainer Doemer, Daniel D. Gajski, and Adnreas Gerstlauer, SpecC Methodology for High-level Modeling, IEEE/DATC Electronic Design Processes Workshop, 2002.
-
(2002)
-
-
Doemer, R.1
Gajski, D.D.2
Gerstlauer, A.3
-
57
-
-
34547995122
-
Towards Performance-oriented Pattern-based Refinement of Synchronous Models onto NoC Communication
-
August
-
Zhonghi Lu et al., Towards Performance-oriented Pattern-based Refinement of Synchronous Models onto NoC Communication, in 9th Euromicro Conf. on Digital System Design (DSD 2006), August 2006.
-
(2006)
in 9th Euromicro Conf. on Digital System Design, (DSD 2006)
-
-
Lu, Z.1
-
58
-
-
0347761332
-
System Modeling and Transformational Design Refinement in ForSyDe
-
January
-
Ingo Sander and Axel Jantsch, System Modeling and Transformational Design Refinement in ForSyDe, IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, Vol. 23, No. 1, January 2004, pp. 17-32.
-
(2004)
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems
, vol.23
, Issue.1
, pp. 17-32
-
-
Sander, I.1
Jantsch, A.2
-
60
-
-
34548814965
-
A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip
-
Digest of Technical Papers, IEEE Intl. Solid State Circuits Conf.
-
Lattard, Didier et al., A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip, Digest of Technical Papers, IEEE Intl. Solid State Circuits Conf., pp. 258-601, 2007.
-
(2007)
, pp. 258-601
-
-
Lattard, D.1
-
61
-
-
0034848112
-
Route Packets, Not Wires: On-Chip Interconnection Networks
-
June
-
Dally, W. J., Towles, B., Route Packets, Not Wires: On-Chip Interconnection Networks, IEEE Proc. Design Automation Conf., pp. 684-689, June 2001.
-
(2001)
IEEE Proc. Design Automation Conf.
, pp. 684-689
-
-
Dally, W.J.1
Towles, B.2
-
62
-
-
0036149420
-
Networks on Chips: A New SoC Paradigm
-
Luca Benini and Giovanni De Micheli, Networks on Chips: A New SoC Paradigm, IEEE Computer, Vol. 35, pp. 70-78, 2002.
-
(2002)
IEEE Computer
, vol.35
, pp. 70-78
-
-
Benini, L.1
Micheli, G.D.2
-
63
-
-
0036505033
-
The Raw microprocessor: a computational fabric for software circuits and general-purpose programs
-
MarchApril
-
Taylor, M.B., et al., The Raw microprocessor: a computational fabric for software circuits and general-purpose programs, IEEE Micro, Vol. 22, Issue 2, pp. 25-35, MarchApril 2002.
-
(2002)
IEEE Micro
, vol.22
, Issue.2
, pp. 25-35
-
-
Taylor, M.B.1
-
64
-
-
33646388655
-
A 155-mW 50M vertices/s graphics processor with fixed-point programmable vertex shader fro mobile applications
-
Ju-Ho Sohn et al., A 155-mW 50M vertices/s graphics processor with fixed-point programmable vertex shader fro mobile applications, IEEE J. Solid-State Circuits, Vol. 41, Issue 5, pp. 1081-1091, 2006.
-
(2006)
IEEE J. Solid-State Circuits
, vol.41
, Issue.5
, pp. 1081-1091
-
-
Sohn, J.-H.1
-
65
-
-
0019009078
-
OSI Reference Model-The ISO Model of Architecture for Open Systems Interconnection
-
April
-
Hubert Zimmermann, OSI Reference Model-The ISO Model of Architecture for Open Systems Interconnection, IEEE Transactions on Communications, Vol. 28, no. 4, April 1980, pp. 425-432.
-
(1980)
IEEE Transactions on Communications
, vol.28
, Issue.4
, pp. 425-432
-
-
Zimmermann, H.1
-
67
-
-
0038645161
-
An 800 MHz star-connected on-chip network for application to systems on a chip
-
February
-
Se-Joong Lee et al., An 800 MHz star-connected on-chip network for application to systems on a chip, IEEE Int. Solid-States Circuits Conf., Digest of Technical papers, pp. 468-469, February 2003.
-
(2003)
IEEE Int. Solid-States Circuits Conf., Digest of Technical papers
, pp. 468-469
-
-
Lee, S.-J.1
-
68
-
-
13144293111
-
A robust self-calibrating transmission scheme for on-chip networks
-
Worn, F., Lenne, P., Thiran, P., De Micheli G., A robust self-calibrating transmission scheme for on-chip networks, IEEE Transactions on VLSI Systems, Vol. 13, Issue 1, pp. 126-139, 2005.
-
(2005)
IEEE Transactions on VLSI Systems
, vol.13
, Issue.1
, pp. 126-139
-
-
Worn, F.1
Lenne, P.2
Thiran, P.3
De Micheli, G.4
-
69
-
-
36349024692
-
Bi-synchronous FIFO for synchronous circuit communication well suited for Network-on-Chip in GALS architectures
-
May
-
Ivan Miro Panades and Alain Greiner, Bi-synchronous FIFO for synchronous circuit communication well suited for Network-on-Chip in GALS architectures, Proc. 1st IEEE/ACM Int. Symp. on Networks-on-Chip, pp. 83-92, May, 2007.
-
(2007)
Proc. 1st IEEE/ACM Int. Symp. on Networks-on-Chip
, pp. 83-92
-
-
Panades, I.M.1
Greiner, A.2
-
70
-
-
84893753441
-
Trade offs in the design a router with both guaranteed and best-effort services for networks on chip
-
Rijpkema E., Trade offs in the design a router with both guaranteed and best-effort services for networks on chip, Design, Automation and Test in Europe Conference and Exhibition, pp. 350-355, 2003.
-
(2003)
Design, Automation and Test in Europe Conference and Exhibition
, pp. 350-355
-
-
Rijpkema, E.1
-
71
-
-
33947117181
-
An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip
-
Kwanho Kim et al., An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip, Proc. IEEE Int. Symp. on Circuits and Systems, pp. 2357-2360, 2005.
-
(2005)
Proc. IEEE Int. Symp. on Circuits and Systems
, pp. 2357-2360
-
-
Kim, K.1
-
72
-
-
85128639946
-
MicroNetwork-Based Integration for SOCs
-
June
-
Wingrad, D., MicroNetwork-Based Integration for SOCs, Proc. Design Automation Conf., pp. 63-677, June 2001.
-
(2001)
Proc. Design Automation Conf.
, pp. 63-677
-
-
Wingrad, D.1
-
73
-
-
2342620693
-
The Nostrum backbone-a Communication Protocol Stack for Network on Chip
-
M. Millberg, et al., The Nostrum backbone-a Communication Protocol Stack for Network on Chip, Proc. Int. Conf. on VLSI Design, pp. 693-696, 2004.
-
(2004)
Proc. Int. Conf. on VLSI Design
, pp. 693-696
-
-
Millberg, M.1
-
74
-
-
33645011974
-
Low-power network-on-chip for high-performance SoC design
-
February
-
Kangmin Lee et al., Low-power network-on-chip for high-performance SoC design, IEEE Transactions on VLSI systems, Vol. 14, pp. 148-160, February 2006.
-
(2006)
IEEE Transactions on VLSI systems
, vol.14
, pp. 148-160
-
-
Lee, K.1
-
75
-
-
22244486343
-
Packet-switched on-chip interconnection network for system-on- chip applications
-
June
-
Se-Joong Lee et al., Packet-switched on-chip interconnection network for system-on- chip applications, IEEE Transactions Circuits and Systems II, Vol. 52, pp. 308-312, June 2005.
-
(2005)
IEEE Transactions Circuits and Systems II
, vol.52
, pp. 308-312
-
-
Lee, S.-J.1
-
76
-
-
27344440896
-
Adaptive network-on-chip with wave-front train serialization scheme
-
June
-
Se-Joong Lee et al., Adaptive network-on-chip with wave-front train serialization scheme, in IEEE Symp. on VLSI Circuits Digest of Technical Papers, pp. 104-107, June 2005.
-
(2005)
in IEEE Symp. on VLSI Circuits Digest of Technical Papers
, pp. 104-107
-
-
Lee, S.-J.1
-
77
-
-
0026981687
-
VLSI Implementation of a 256 x 256 Crossbar Interconnection Network
-
Kyusun Choi and William S. Adams, VLSI Implementation of a 256 x 256 Crossbar Interconnection Network, Proc. IEEE 6th Int. Parallel Processing Symp., pp. 289-293, 1992.
-
(1992)
Proc. IEEE 6th Int. Parallel Processing Symp.
, pp. 289-293
-
-
Choi, K.1
Adams, W.S.2
-
79
-
-
4444335188
-
SUNMAP: A Tool for Automatic Topology Selection and Generation for NOCs
-
Murali, S., et al., SUNMAP: A Tool for Automatic Topology Selection and Generation for NOCs, in Proc. Design Automation Conf., 2004, pp. 914-919.
-
(2004)
in Proc. Design Automation Conf.
, pp. 914-919
-
-
Murali, S.1
-
80
-
-
33645002018
-
A Technology-aware and Energy-oriented Topology Exploration for On-chip Networks
-
Wang, H., et al., A Technology-aware and Energy-oriented Topology Exploration for On-chip Networks, in Proc. Conf. on Design Automation and Test in Europe, 2005, pp. 1238-1243.
-
(2005)
in Proc. Conf. on Design Automation and Test in Europe
, pp. 1238-1243
-
-
Wang, H.1
-
81
-
-
44149127082
-
Energy and Latency Evaluation of NoC Topologies
-
Kreutz, M., et al., Energy and Latency Evaluation of NoC Topologies, in Proc. Int. Symp. on Circuits and Systems, 2005, pp. 5866-5869.
-
(2005)
in Proc. Int. Symp. on Circuits and Systems
, pp. 5866-5869
-
-
Kreutz, M.1
-
82
-
-
27244443947
-
A 600MIPS 120 mW 70 pA Leakage Triple-CPU Mobile Application Processor Chip
-
Torii, S., et al., A 600MIPS 120 mW 70 pA Leakage Triple-CPU Mobile Application Processor Chip, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2005, pp. 136-137.
-
(2005)
in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers
, pp. 136-137
-
-
Torii, S.1
-
84
-
-
2442698800
-
A 51 mW 1.6 GHz On-Chip Network for Low-Power Heterogeneous SoC Platform
-
Kangmin Lee et al., A 51 mW 1.6 GHz On-Chip Network for Low-Power Heterogeneous SoC Platform, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2004, pp. 152-153.
-
(2004)
in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers
, pp. 152-153
-
-
Lee, K.1
-
85
-
-
33645002018
-
A Technology-aware and Energy-oriented Topology Exploration for On-chip Networks
-
Wang, H., et al., A Technology-aware and Energy-oriented Topology Exploration for On-chip Networks, in Proc. Conf. on Design Automation and Test in Europe, 2005, pp. 1238-1243.
-
(2005)
in Proc. Conf. on Design Automation and Test in Europe
, pp. 1238-1243
-
-
Wang, H.1
-
86
-
-
33947117181
-
An Arbitration Look-Ahead Scheme for Reducing End-to-end Latency in Networks on Chip
-
May
-
Kim, K., et al., An Arbitration Look-Ahead Scheme for Reducing End-to-end Latency in Networks on Chip, Proc. of Int. Symp. on Circuits and Systems, May 2005, pp. 2357-2360.
-
(2005)
Proc. of Int. Symp. on Circuits and Systems
, pp. 2357-2360
-
-
Kim, K.1
-
87
-
-
85128675060
-
Cost-Optimized System-on-Chip Implementation with On-Chip Network
-
Doctoral Dissertation
-
Se-Joong Lee, Cost-Optimized System-on-Chip Implementation with On-Chip Network, Doctoral Dissertation, http://ssl.kaist.ac.kr/.
-
-
-
Lee, S.-J.1
-
88
-
-
0003794137
-
-
(2nd ed.), Prentice-Hall International Editions
-
D. Bertsekas and R. Gallager, Data Networks (2nd ed.), Prentice-Hall International Editions, 1992, pp. 93-97.
-
(1992)
Data Networks
, pp. 93-97
-
-
Bertsekas, D.1
Gallager, R.2
-
89
-
-
0032655137
-
The iSLIP scheduling algorithm for input-queued switches
-
Mckeown, N., The iSLIP scheduling algorithm for input-queued switches, IEEE/ACM Transactions on Networking, Vol. 7, Issue 2, pp. 188-201, 1999.
-
(1999)
IEEE/ACM Transactions on Networking
, vol.7
, Issue.2
, pp. 188-201
-
-
Mckeown, N.1
-
90
-
-
0242611691
-
A distributed crossbar switch scheduler for on-chip networks
-
Sept.
-
Kangmin Lee, Se-joong Lee, and Hoi-Jun Yoo, A distributed crossbar switch scheduler for on-chip networks, IEEE Proc. Custom Integrated Circuits Conf., pp. 671-674, Sept., 2003.
-
(2003)
IEEE Proc. Custom Integrated Circuits Conf.
, pp. 671-674
-
-
Lee, K.1
Lee, S.-J.2
Yoo, H.-J.3
-
94
-
-
35048834531
-
Bus-Invert Coding for Low-Power I/O
-
March
-
Stan, M. R., et al., Bus-Invert Coding for Low-Power I/O, IEEE Trans. VLSI systems, Vol. 3, pp. 49-58, March 1995.
-
(1995)
IEEE Trans. VLSI systems
, vol.3
, pp. 49-58
-
-
Stan, M.R.1
-
96
-
-
0030644909
-
Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems
-
March
-
Benini, L., et al., Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems, in Proc. of Great Lakes Symp. on VLSI, March 1997, pp. 77-82.
-
(1997)
in Proc. of Great Lakes Symp. on VLSI
, pp. 77-82
-
-
Benini, L.1
-
97
-
-
0031623210
-
Partial Bus-Invert Coding for Power Optimization of System Level Bus
-
Aug
-
Shin, Y., et al., Partial Bus-Invert Coding for Power Optimization of System Level Bus, in Proc. of Int. Symp. on Low Power Electronics and Design, Aug. 1998, pp. 127-129.
-
(1998)
in Proc. of Int. Symp. on Low Power Electronics and Design
, pp. 127-129
-
-
Shin, Y.1
-
98
-
-
0032628047
-
A Coding Framework for Low-Power Address and Data Busses
-
June
-
Ramprasad, S., et al., A Coding Framework for Low-Power Address and Data Busses, IEEE Trans. VLSI systems, Vol. 7, pp. 212-221, June 1999.
-
(1999)
IEEE Trans. VLSI systems
, vol.7
, pp. 212-221
-
-
Ramprasad, S.1
-
99
-
-
3042651389
-
Why Transition Coding for Power Minimization of on-Chip Buses does not work
-
February
-
Kretzschmar, C., et al., Why Transition Coding for Power Minimization of on-Chip Buses does not work, in Proc. of the Design Automation and Test Europe Conf. (DATE), February 2004, pp. 512-517.
-
(2004)
in Proc. of the Design Automation and Test Europe Conf. (DATE)
, pp. 512-517
-
-
Kretzschmar, C.1
-
100
-
-
0035472993
-
Narrow Bus Encoding for Low-Power DSP Systems
-
October
-
Shin, Y., et al., Narrow Bus Encoding for Low-Power DSP Systems, IEEE Trans. VLSI systems, Vol. 9, pp. 656-660, October 2001.
-
(2001)
IEEE Trans. VLSI systems
, vol.9
, pp. 656-660
-
-
Shin, Y.1
-
101
-
-
0038645161
-
An 800MHz star-connected on-chip network for application to systems on a chip
-
Lee, S., et al., An 800MHz star-connected on-chip network for application to systems on a chip, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2003, pp. 468-469.
-
(2003)
in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers
, pp. 468-469
-
-
Lee, S.1
-
102
-
-
33645011974
-
Low-power network-on-chip for high-performance SoC design
-
February
-
Lee, K., et al., Low-power network-on-chip for high-performance SoC design, IEEE Trans. VLSI systems, Vol. 14, February 2006, pp. 148-160.
-
(2006)
IEEE Trans. VLSI systems
, vol.14
, pp. 148-160
-
-
Lee, K.1
-
103
-
-
16244392403
-
SILENT: serialized low energy transmission coding for on-chip interconnection networks
-
Lee, K., et al., SILENT: serialized low energy transmission coding for on-chip interconnection networks, in ACM/IEEE Int. Conf. on Computer-Aided Design, 2004, pp. 448-451.
-
(2004)
in ACM/IEEE Int. Conf. on Computer-Aided Design
, pp. 448-451
-
-
Lee, K.1
-
105
-
-
0033704034
-
Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness
-
June
-
Zhang, H., et al., Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness, IEEE Trans. VLSI systems, Vol. 8, June 2000, pp. 264-272.
-
(2000)
IEEE Trans. VLSI systems
, vol.8
, pp. 264-272
-
-
Zhang, H.1
-
106
-
-
0002491518
-
High Performance Level Restoration Circuits for Low-Power Reduced-swing Interconnection Schemes
-
December
-
Moisiadis, Y., et al., High Performance Level Restoration Circuits for Low-Power Reduced-swing Interconnection Schemes, in Proc. of Int. Conf on Electronics Circuits and Systems, December 2000, pp. 619-622.
-
(2000)
in Proc. of Int. Conf on Electronics Circuits and Systems
, pp. 619-622
-
-
Moisiadis, Y.1
-
107
-
-
0028585205
-
A novel reduced swing CMOS BUS interface circuit for high speed low power VLSI systems
-
May
-
Golshan, R., et al., A novel reduced swing CMOS BUS interface circuit for high speed low power VLSI systems, in Proc. of IEEE Int. Symp. Circuits and Systems, May 1994, pp. 351-354.
-
(1994)
in Proc. of IEEE Int. Symp. Circuits and Systems
, pp. 351-354
-
-
Golshan, R.1
-
108
-
-
0027575799
-
Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's
-
April
-
Nakagome, Y., et al., Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's, IEEE J. of Solid-State Circuits, Vol. 28, pp. 414-419, April 1993.
-
(1993)
IEEE J. of Solid-State Circuits
, vol.28
, pp. 414-419
-
-
Nakagome, Y.1
-
110
-
-
0029289214
-
Data-Dependent Logic Swing Internal Bus Architecture for Ultralow- Power LSI's
-
April
-
Hiraki, M., et al., Data-Dependent Logic Swing Internal Bus Architecture for Ultralow- Power LSI's, IEEE J. of Solid-State Circuits, Vol. 30, pp. 397-402, April 1995.
-
(1995)
IEEE J. of Solid-State Circuits
, vol.30
, pp. 397-402
-
-
Hiraki, M.1
-
111
-
-
27344452711
-
Analysis and Implementation of Practical, Cost-Effective Networks on Chips
-
September
-
Lee, S., et al., Analysis and Implementation of Practical, Cost-Effective Networks on Chips, IEEE Design and Test of Computers, September 2005, pp. 422-433.
-
(2005)
IEEE Design and Test of Computers
, pp. 422-433
-
-
Lee, S.1
-
112
-
-
0035392122
-
Optimum Voltage Swing on On-Chip and Off-Chip interconnect
-
July
-
Svensson, C., Optimum Voltage Swing on On-Chip and Off-Chip interconnect, IEEE J. of Solid-State Circuits, Vol. 36, pp. 1108-1112, July 2001.
-
(2001)
IEEE J. of Solid-State Circuits
, vol.36
, pp. 1108-1112
-
-
Svensson, C.1
-
113
-
-
13144293111
-
A Robust Self-Calibrating Transmission Scheme for On-Chip Networks
-
January
-
Worm, F., et al., A Robust Self-Calibrating Transmission Scheme for On-Chip Networks, IEEE Trans. VLSI systems, vol. 13, pp. 126-139, January 2005.
-
(2005)
IEEE Trans. VLSI systems
, vol.13
, pp. 126-139
-
-
Worm, F.1
-
114
-
-
2442698800
-
A 51mW 1.6GHz On-Chip Network for Low-Power Heterogeneous SoC Platform
-
Lee, K., et al., A 51mW 1.6GHz On-Chip Network for Low-Power Heterogeneous SoC Platform, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2004, pp. 152-153.
-
(2004)
in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers
, pp. 152-153
-
-
Lee, K.1
-
115
-
-
0037225560
-
A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers
-
January-February
-
Wang, H. S., et al., A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers, IEEE Micro, Vol. 23, No. 1, January-February 2003, pp. 26-35.
-
(2003)
IEEE Micro
, vol.23
, Issue.1
, pp. 26-35
-
-
Wang, H.S.1
-
117
-
-
0037776698
-
High speed asynchronous structures for inter-clocking domain communication
-
Chattopadhyay, A., et al., High speed asynchronous structures for inter-clocking domain communication, Int. Conf. on Electronics, Circuits and Systems, 2002, pp. 517-520.
-
(2002)
Int. Conf. on Electronics, Circuits and Systems
, pp. 517-520
-
-
Chattopadhyay, A.1
-
119
-
-
34548858682
-
An 80-Tile 1.28TFLOPS Network-on-chip in 65nm CMOS
-
Sriram Vangal et al., An 80-Tile 1.28TFLOPS Network-on-chip in 65nm CMOS, ISSCC 2007, pp. 98-99.
-
(2007)
ISSCC
, pp. 98-99
-
-
Vangal, S.1
-
120
-
-
0004257733
-
-
Cambridge University Press, Cambridge
-
Dally, W. J., Poulton, J. H., Digital Systems Engineering, Cambridge University Press, Cambridge, 1998.
-
(1998)
Digital Systems Engineering
-
-
Dally, W.J.1
Poulton, J.H.2
-
121
-
-
27344440896
-
Adaptive Network-on-Chip with Wave-Front Train Serialization Scheme
-
June
-
Lee, S., et al., Adaptive Network-on-Chip with Wave-Front Train Serialization Scheme, in IEEE Symp. on VLSI Circuits Dig. Tech. Papers, June 2005, pp. 104-107.
-
(2005)
in IEEE Symp. on VLSI Circuits Dig. Tech. Papers
, pp. 104-107
-
-
Lee, S.1
-
122
-
-
0037631130
-
A 210mW Graphics LSI Implementing Full 3D Pipeline with 264Mtex- els/s Texturing for Mobile Multimedia Applications
-
Woo, R., et al., A 210mW Graphics LSI Implementing Full 3D Pipeline with 264Mtex- els/s Texturing for Mobile Multimedia Applications, ISSCC Dig. of Tech. Papers, pp. 44-45, 2003.
-
(2003)
ISSCC Dig. of Tech. Papers
, pp. 44-45
-
-
Woo, R.1
-
123
-
-
0034771116
-
Current-sensing for crossbars
-
Sinha, M., et al., Current-sensing for crossbars, IEEE Int. ASIC/SOC Conf. 2001, pp. 25-29.
-
(2001)
IEEE Int. ASIC/SOC Conf.
, pp. 25-29
-
-
Sinha, M.1
-
125
-
-
24144490066
-
Design and Implementing a Fast Crossbar Scheduler
-
January
-
Gupta, P., et al., Design and Implementing a Fast Crossbar Scheduler, IEEE Micro, Vol. 19, pp. 20-28, January 1999.
-
(1999)
IEEE Micro
, vol.19
, pp. 20-28
-
-
Gupta, P.1
-
126
-
-
0026123859
-
A Variable Round-Robin Arbiter for High Speed Buses and Statistical Multiplexes
-
March
-
Lee, K., et al., A Variable Round-Robin Arbiter for High Speed Buses and Statistical Multiplexes, in Proc. Int. Phoenix Conference on Computers and Communications, March 1991, pp. 23-29.
-
(1991)
in Proc. Int. Phoenix Conference on Computers and Communications
, pp. 23-29
-
-
Lee, K.1
-
127
-
-
0036948803
-
Round-robin Arbiter Design and Generation
-
October
-
Shin, E., et al., Round-robin Arbiter Design and Generation, in Proc. IEEE Int. Symp. System Synthesis, pp. 243-248, October 2002.
-
(2002)
in Proc. IEEE Int. Symp. System Synthesis
, pp. 243-248
-
-
Shin, E.1
-
128
-
-
34547211508
-
Evaluation and Design TradeOffs Between Circuit Switched and Packet Switched NOCs for Application-Specific SOCs
-
KueiChung Chang, JihSheng Shen, and TienFu Chen, Evaluation and Design TradeOffs Between Circuit Switched and Packet Switched NOCs for Application-Specific SOCs, in Proc. Design Automation Conference, 2006, pp. 143-148.
-
(2006)
in Proc. Design Automation Conference
, pp. 143-148
-
-
Chang, K.C.1
Shen, J.S.2
Chen, T.F.3
-
129
-
-
0038645161
-
An 800MHz star-connected on-chip network for application to systems on a chip
-
Lee, S., et al., An 800MHz star-connected on-chip network for application to systems on a chip, IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2003, pp. 468-469.
-
(2003)
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers
, pp. 468-469
-
-
Lee, S.1
-
130
-
-
22244486343
-
Packet-Switched On-Chip Interconnection Network for System-on-Chip Applications
-
June
-
Lee, S., et al., Packet-Switched On-Chip Interconnection Network for System-on-Chip Applications, IEEE Transactions on Circuits and Systems II, Vol. 52, No. 6, pp. 308312, June 2005.
-
(2005)
IEEE Transactions on Circuits and Systems II
, vol.52
, Issue.6
, pp. 308-312
-
-
Lee, S.1
-
131
-
-
0242611691
-
A Distributed On-Chip Crossbar Switch Scheduler for On-Chip Network
-
September
-
Lee, K., et al., A Distributed On-Chip Crossbar Switch Scheduler for On-Chip Network, IEEE Custom Integrated Circuits Conf., September 2003, pp. 671-674.
-
(2003)
IEEE Custom Integrated Circuits Conf.
, pp. 671-674
-
-
Lee, K.1
-
132
-
-
2442698800
-
A 51 mW 1.6G Hz On-Chip Network for Low-Power Heterogeneous SoC Platform
-
Lee, K., et al., A 51 mW 1.6G Hz On-Chip Network for Low-Power Heterogeneous SoC Platform, In IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2004, pp. 152-153.
-
(2004)
In IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers
, pp. 152-153
-
-
Lee, K.1
-
133
-
-
16244392403
-
SILENT: serialized low energy transmission coding for on-chip interconnection networks
-
Lee, K., et al., SILENT: serialized low energy transmission coding for on-chip interconnection networks, In ACM/IEEE Int. Conf. on Computer-Aided Design, 2004, pp. 448-451.
-
(2004)
In ACM/IEEE Int. Conf. on Computer-Aided Design
, pp. 448-451
-
-
Lee, K.1
-
134
-
-
14844320514
-
Low Energy Transmission Coding for On-Chip Serial Communications
-
September
-
Lee, K., et al., Low Energy Transmission Coding for On-Chip Serial Communications, IEEEInt. SOC Conf., September 2004, pp. 177-178.
-
(2004)
IEEEInt. SOC Conf.
, pp. 177-178
-
-
Lee, K.1
-
135
-
-
34250743082
-
Networks-on-Chip and Networks-in-Package for High-Performance SoC Platforms
-
Nov
-
Lee, K., et al., Networks-on-Chip and Networks-in-Package for High-Performance SoC Platforms, IEEE Asian Solid Stated Circuits Conf., Nov. 2005, pp. 485-488.
-
(2005)
IEEE Asian Solid Stated Circuits Conf.
, pp. 485-488
-
-
Lee, K.1
-
136
-
-
33645011974
-
Low-power network-on-chip for high-performance SoC design
-
Feb
-
Lee, K., et al., Low-power network-on-chip for high-performance SoC design, IEEE Trans. VLSI systems, Vol. 14, Feb 2006, pp. 148-160.
-
(2006)
IEEE Trans. VLSI systems
, vol.14
, pp. 148-160
-
-
Lee, K.1
-
137
-
-
27344440896
-
Adaptive Network-on-Chip with Wave-Front Train Serialization Scheme
-
June
-
Lee, S., et al., Adaptive Network-on-Chip with Wave-Front Train Serialization Scheme, In IEEE Symp. on VLSI Circuits Dig. Tech. Papers, June 2005, pp. 104-107.
-
(2005)
In IEEE Symp. on VLSI Circuits Dig. Tech. Papers
, pp. 104-107
-
-
Lee, S.1
-
138
-
-
27344452711
-
Analysis and Implementation of Practical, Cost-Effective Networks on Chips
-
September
-
Lee, S., et al., Analysis and Implementation of Practical, Cost-Effective Networks on Chips, IEEE Design and Test of Computers, September 2005, pp. 422-433.
-
(2005)
IEEE Design and Test of Computers
, pp. 422-433
-
-
Lee, S.1
-
139
-
-
33745771059
-
A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on-Chip
-
May
-
Kim, D., et al., A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on-Chip, Int. Symposium on Circuits and Systems, May 2005, pp. 2369-2372.
-
(2005)
Int. Symposium on Circuits and Systems
, pp. 2369-2372
-
-
Kim, D.1
-
140
-
-
33947117181
-
An Arbitration Look-Ahead Scheme for Reducing End-to-End Latency in Networks-on-Chip
-
May
-
Kim, K., et al., An Arbitration Look-Ahead Scheme for Reducing End-to-End Latency in Networks-on-Chip, Int. Symposium on Circuits and Systems, May 2005, pp. 2357-2360.
-
(2005)
Int. Symposium on Circuits and Systems
, pp. 2357-2360
-
-
Kim, K.1
-
141
-
-
28144456407
-
A Chip-Package Hybrid DLL Loop and Clock Distribution Network for Low-Jitter Clock Delivery
-
February
-
Chung, D., et al., A Chip-Package Hybrid DLL Loop and Clock Distribution Network for Low-Jitter Clock Delivery, IEEE Int. Solid-State Circuits Conf., February 2005, pp. 514-515.
-
(2005)
IEEE Int. Solid-State Circuits Conf.
, pp. 514-515
-
-
Chung, D.1
-
142
-
-
28144460105
-
A 50M vertices/s Graphics Processor with Fixed-Point Programmable Vertex Shader for Mobile Applications
-
February
-
Sohn, J.-H., et al., A 50M vertices/s Graphics Processor with Fixed-Point Programmable Vertex Shader for Mobile Applications, IEEE Int. Solid-State Circuits Conf., February 2005, pp. 192-193.
-
(2005)
IEEE Int. Solid-State Circuits Conf.
, pp. 192-193
-
-
Sohn, J.-H.1
-
143
-
-
36348960161
-
Circuits, Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC
-
May
-
Kim, D., et. al, Circuits, Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC, In Proc. of IEEE International Symposium on Networks-on-Chip (NOCS), pp. 30-39, May 2007.
-
(2007)
In Proc. of IEEE International Symposium on Networks-on-Chip (NOCS)
, pp. 30-39
-
-
Kim, D.1
-
144
-
-
3042535216
-
Distinctive Image Features from Scale-Invariant Keypoints
-
Lowe, D. G., Distinctive Image Features from Scale-Invariant Keypoints, ACM International Journal of Computer Vision. Vol. 60, Issue 2, pp. 91-110. 2004.
-
(2004)
ACM International Journal of Computer Vision
, vol.60
, Issue.2
, pp. 91-110
-
-
Lowe, D.G.1
-
145
-
-
34548716845
-
From a Few Cores to Many: A Tera-scale Computing Research Overview, white paper
-
Intel Corporation
-
Held, J., et al., From a Few Cores to Many: A Tera-scale Computing Research Overview, white paper, Intel Corporation, www.intel.com.
-
-
-
Held, J.1
-
147
-
-
33745160052
-
A Six-Port 57GB/s Double-Pumped Non-blocking Router Core
-
June
-
Vangal, S., Borkar, N. Y., Alvandpour, A., A Six-Port 57GB/s Double-Pumped Non-blocking Router Core, Dig. Symp. VLSI Circuits, pp. 268-269, June 2005.
-
(2005)
Dig. Symp. VLSI Circuits
, pp. 268-269
-
-
Vangal, S.1
Borkar, N.Y.2
Alvandpour, A.3
-
148
-
-
0242720765
-
Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors
-
November
-
Tschanz, J., Narendra, S. G., Ye, Y., et al., Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors, IEEE J. Solid-State Circuits, pp. 1838-1845, November 2003.
-
(2003)
IEEE J. Solid-State Circuits
, pp. 1838-1845
-
-
Tschanz, J.1
Narendra, S.G.2
Ye, Y.3
-
149
-
-
34548822802
-
A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS
-
February
-
Khellah, M., Kim, N. S., Howard, J., et al., A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS, ISSCC Dig. Tech. Papers, pp. 624-625, February 2006.
-
(2006)
ISSCC Dig. Tech. Papers
, pp. 624-625
-
-
Khellah, M.1
Kim, N.S.2
Howard, J.3
-
151
-
-
20344365592
-
Application of the Intel® Reconfigurable Communications Architecture to 802.11a, 3G and 4G Standards
-
May 31-June 2
-
Chun, A., et al., Application of the Intel® Reconfigurable Communications Architecture to 802.11a, 3G and 4G Standards, Frontiers of Mobile and Wireless Communication, May 31-June 2, 2004.
-
(2004)
Frontiers of Mobile and Wireless Communication
-
-
Chun, A.1
|