Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning

Design Automation for Embedded Systems

Volumn 2, Issue 2, 1997, Pages 237-261

  Vahid, Frank ^a   Le, Thuy Dm ^a  

^a University of California ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; COMPUTER CIRCUITS; COMPUTER HARDWARE; COMPUTER SOFTWARE; DATA STRUCTURES; GRAPH THEORY; HEURISTIC METHODS; PROBLEM SOLVING;

CIRCUIT PARTITIONING; KERNIGHAN-LIN HEURISTIC;

COMPUTER SYSTEMS;

EID: 0031099473     PISSN: 09295585     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008836303344     Document Type: Article

References (26)

1. P. Athanas and H. Silverman. Processor reconfiguration through instruction-set metamorphosis. IEEE Computer 26: 11-18, March 1993.
2. R. Hartenstein, J. Becker, and R. Kress. Two-level partitioning of image processing algorithms for the parallel map-oriented machine. In International Workshop on Hardware-Software Co-Design, pp. 77-84. 1996.
3. R. Ernst, J. Henkel, and T. Benner. Hardware-software cosynthesis for microcontrollers. In IEEE Design & Test of Computers, pp. 64-75, December 1994.
4. R. Gupta and G. DeMicheli. Hardware-software cosynthesis for digital systems. In IEEE Design & Test of Computers, pp. 29-41, October 1993.
5. D. Gajski, F. Vahid, S. Narayan, and J. Gong. Specification and Design of Embedded Systems. Prentice Hall, New Jersey, 1994.
6. F. Vahid, T. Le, and Y. Hsu. A comparison of functional and structural partitioning. In International Symposium on System Synthesis, pp. 121-126, 1996.
7. X. Xiong, E. Barros, and W. Rosentiel. A method for partitioning UNITY language in hardware and software. In Proceedings of the European Design Automation Conference (EuroDAC), 1994.
8. A. Kalavade and E. Lee. A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem. In International Workshop on Hardware-Software Co-Design, pp. 42-48, 1994.
9. P. Knudsen and J. Madsen. PACE: A dynamic programming algorithm for hardware/software partitioning. In International Workshop on Hardware-Software Co-Design, pp. 85-92, 1996.
10. A. Balboni, W. Fornaciari, and D. Sciuto. Partitioning and exploration strategies in the tosca co-design flow. In International Workshop on Hardware-Software Co-Design, pp. 62-69, 1993.
11. F. Vahid and D. Gajski. Closeness metrics for system-level functional partitioning. In Proceedings of the European Design Automation Conference (EuroDAC), pp. 328-333, 1995.
12. D. Gajski, S. Narayan, L. Ramachandran, F. Vahid, and P. Fung. System design methodologies: Aiming at the 100 h design cycle. IEEE Transactions on Very Large Scale Integration Systems 4(1): 70-82, 1996.
13. W. Wolf. Hardware-software co-design of embedded systems. Proceedings of the IEEE 82(7): 967-989, 1994.
14. D. Gajski and F. Vahid. Specification and design of embedded hard ware-software systems. IEEE Design & Test of Computers 12(1): 53-67, 1995.
15. B. Kernighan and S. Lin. An efficient heuristic procedure for partitioning graphs. Bell System Technical Journal, February 1970.
16. T. Lengauer. Combinatorial Algorithms for Integrated Circuit Layout. John Wiley and Sons, England, 1990.
17. C. Fiduccia and R. Mattheyses. A linear-time heuristic for improving network partitions. In Proceedings of the Design Automation Conference, 1982.
18. F. Vahid and D. Gajski. SLIF: A specification-level intermediate format for system design. In Proceedings of the European Design and Test Conference (EDTC), pp. 185-189, 1995.
19. F. Vahid. Procedure exlining: A transformation for improved system and behavioral synthesis. In International Symposium on System Synthesis, pp. 84-89, 1995.
20. J. Gong, D. Gajski, and S. Narayan. Software estimation using a generic processor model. In Proceedings of the European Design and Test Conference (EDTC), pp. 498-502, 1995.
21. F. Vahid and D. Gajski. Incremental hardware estimation during hardware/software functional partitioning. IEEE Transactions on Very Large Scale Integration Systems 3(3): 459-464, 1995.
22. S. Kirkpatrick, C. Gelatt, and M. P. Vecchi. Optimization by simulated annealing. Science 220(4598): 671-680, 1983.
23. B. Krishnamurthy. An improved min-cut algorithm for partitioning VLSI networks. IEEE Transactions on Computers, May 1984.
24. L. Sanchis. Multiple-way network partitioning. IEEE Transactions on Computer-Aided Design, January 1989.
25. S. Narayan and D. Gajski. Synthesis of system-level bus interfaces. In Proceedings of the European Conference on Design Automation (EDAC), 1994.
26. F. Vahid and T. Le. Towards a model for hardware and software functional partitioning. In International Workshop on Hardware-Software Co-Design, pp. 116-123, 1996.