Bi-synchronous FIFO for synchronous circuit communication well suited for network-on-chip in GALS architectures

Proceedings - NOCS 2007: First International Symposium on Networks-on-Chip

Volumn , Issue , 2007, Pages 83-92

  Miro Panades, Ivan ^a   Greiner, Alain ^b  

^a STMICROELECTRONICS   (France)

^b SORBONNE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION SYSTEMS; INTERFACES (COMPUTER); THROUGHPUT;

CIRCUIT COMMUNICATION; CLOCK SIGNALS; PROCESS VARIATION; SYNCHRONOUS CIRCUITS; SYNCHRONOUS ISLANDS;

MICROPROCESSOR CHIPS;

EID: 36349024692     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2007.14     Document Type: Conference Paper

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