-
1
-
-
0038001279
-
A 1.3ghz fifth generation sparc64 microprocessor
-
H. Ando et al., "A 1.3GHz Fifth Generation SPARC64 Microprocessor ," Proc. Intl. Solid-State Ciruits Conf., 2003.
-
(2003)
Proc. Intl. Solid-State Ciruits Conf
-
-
Ando, H.1
-
2
-
-
84858199036
-
A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation
-
S. Asaad et al., "A Cycle-accurate, Cycle-reproducible multi-FPGA System for Accelerating Multi-core Processor Simulation," Proc. Intl. Symp. Field Programmable Gate Arrays, 2012
-
(2012)
Proc. Intl. Symp. Field Programmable Gate Arrays
-
-
Asaad, S.1
-
3
-
-
77956595974
-
Verification of soft error detection mechanism through fault injection on hardware emulation platform
-
O. Bailan et al., "Verification of soft error detection mechanism through fault injection on hardware emulation platform," Proc. Intl. Conf. Dependable Systems and Networks Workshops, 2010.
-
(2010)
Proc. Intl. Conf. Dependable Systems and Networks Workshops
-
-
Bailan, O.1
-
4
-
-
45749094585
-
Soft-error resilience of the IBM POWER6 processor input/output subsystem
-
May
-
C. Bender et al., "Soft-error resilience of the IBM POWER6 processor input/output subsystem," IBM Journal of Research and Development, vol. 52, no. 3, May 2008.
-
(2008)
IBM Journal of Research and Development
, vol.52
, Issue.3
-
-
Bender, C.1
-
5
-
-
0345382715
-
SystemC co-simulation and emulation of multi-processor soc designs
-
April
-
L. Benini et al., "SystemC Co-simulation and Emulation of Multi-Processor SoC Designs," IEEE Computer, Vol. 36, No. 4, April 2003.
-
(2003)
IEEE Computer
, vol.36
, Issue.4
-
-
Benini, L.1
-
6
-
-
79953093822
-
-
Ph.D. Dissertation, Princeton University, Princeton, NJ, USA
-
C. Bienia, "Benchmarking Modern MultIProcessors," Ph.D. Dissertation, Princeton University, Princeton, NJ, USA.
-
Benchmarking Modern MultIProcessors
-
-
Bienia, C.1
-
7
-
-
84879873377
-
Quantitative evaluation of soft error injection techniques for robust system design
-
H. Cho et al., "Quantitative Evaluation of Soft Error Injection Techniques for Robust System Design," Proc. Design Automation Conference, 2013.
-
(2013)
Proc. Design Automation Conference
-
-
Cho, H.1
-
9
-
-
0025505949
-
Simulated fault injection: A methodology to evaluate fault tolerant microprocessor architectures
-
Oct
-
G. S. Choi, R. K. Iyer and V. A. Carreno, "Simulated Fault Injection: A Methodology to Evaluate Fault Tolerant Microprocessor Architectures," IEEE Trans. Reliability, vol. 39, no. 4, Oct. 1990.
-
(1990)
IEEE Trans. Reliability
, vol.39
, Issue.4
-
-
Choi, G.S.1
Iyer, R.K.2
Carreno, V.A.3
-
10
-
-
77953106930
-
Vision for cross-layer optimization to address the dual challenges of energy and reliability
-
A. DeHon, H. M. Quinn, and N. P. Carter, "Vision for Cross-Layer Optimization to Address the Dual Challenges of Energy and Reliability," Proc. Design, Automation and Test in Europe, 2010.
-
(2010)
Proc. Design, Automation and Test in Europe
-
-
DeHon, A.1
Quinn, H.M.2
Carter, N.P.3
-
11
-
-
1542359984
-
A hybrid fault injection approach based on simulation and emulation co-operation
-
A. Ejlali et al., "A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation," Proc. Intl. Conf. Dependable Systems and Networks, 2003.
-
(2003)
Proc. Intl. Conf. Dependable Systems and Networks
-
-
Ejlali, A.1
-
12
-
-
0042078549
-
A survey of rollback-recovery protocols in message-passing systems
-
Sep
-
E. N. Elnozahy et al., "A survey of rollback-recovery protocols in message-passing systems," ACM Comput. Surv., vol. 34, no. 3, Sep. 2002.
-
(2002)
ACM Comput. Surv
, vol.34
, Issue.3
-
-
Elnozahy, E.N.1
-
13
-
-
84866616633
-
The forgotten 'uncore': On the energy-efficiency of heterogeneous cores
-
V. Gupta et al., "The Forgotten 'Uncore': On the Energy-efficiency of Heterogeneous Cores," USENIX Annual Technical Conf., 2012.
-
(2012)
USENIX Annual Technical Conf
-
-
Gupta, V.1
-
14
-
-
0031388396
-
DEPEND: A simulation-based environment for system level dependability analysis
-
Jan
-
K. K. Goswami, R. K. Iyer, and L. Young, "DEPEND: A Simulation-Based Environment for System Level Dependability Analysis," IEEE Trans. Computers, vol. 46, no. 1, Jan. 1997.
-
(1997)
IEEE Trans. Computers
, vol.46
, Issue.1
-
-
Goswami, K.K.1
Iyer, R.K.2
Young, L.3
-
15
-
-
84944082071
-
A low-tech solution to avoid the severe impact of transient errors on the IP interconnect
-
D. Graham et al., "A low-tech solution to avoid the severe impact of transient errors on the IP interconnect," Proc. Asia and South Pacific Design Automation Conference, 2009.
-
(2009)
Proc. Asia and South Pacific Design Automation Conference
-
-
Graham, D.1
-
16
-
-
84911203186
-
Reconfigurable computing: The theory and practice of FPGA-based computation
-
S. Hauck and A. Dehon, "Reconfigurable computing: The theory and practice of FPGA-based computation," Morgan Kaufmann, 2010.
-
(2010)
Morgan Kaufmann
-
-
Hauck, S.1
DeHon, A.2
-
17
-
-
84903134651
-
On enhancing power benefits in 3d ics: Block folding and bonding styles perspective
-
M. Jung et al., "On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective," Proc. Design Automation Conference, 2014.
-
(2014)
Proc. Design Automation Conference
-
-
Jung, M.1
-
18
-
-
0033316552
-
Hierarchical simulation approach to accurate fault modeling for system dependability evaluation
-
Sept.-Oct
-
Z. Kalbarczyk et al., "Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation," IEEE Trans. Software Engineering, vol. 25, no. 5, Sept.-Oct. 1999.
-
(1999)
IEEE Trans. Software Engineering
, vol.25
, Issue.5
-
-
Kalbarczyk, Z.1
-
21
-
-
84891503079
-
Self-repair of uncore components in robust system-on-chIPs: An opensparc t2 case study
-
Y. Li et al., "Self-Repair of Uncore Components in Robust System-on-ChIPs: An OpenSPARC T2 Case Study," Proc. IEEE Intl. Test Conf., 2013.
-
(2013)
Proc. IEEE Intl. Test Conf
-
-
Li, Y.1
-
22
-
-
84883132873
-
Single-event performance and layout optimization of flIP-flops in a 28-nm bulk technology
-
Aug
-
K. Lilja et al., "Single-Event Performance and Layout Optimization of FlIP-Flops in a 28-nm Bulk Technology," IEEE Trans. Nucli. Sci., vol. 60, no. 4, Aug. 2013.
-
(2013)
IEEE Trans. Nucli. Sci
, vol.60
, Issue.4
-
-
Lilja, K.1
-
23
-
-
84886743141
-
Transaction level error susceptibility model for bus based soc architectures
-
I.-C. Lin et al., "Transaction Level Error Susceptibility Model for Bus Based SoC Architectures," Proc. Intl. Symp. Quality Electronic Design, 2006.
-
(2006)
Proc. Intl. Symp. Quality Electronic Design
-
-
Lin, I.-C.1
-
24
-
-
84907476418
-
Effective post-silicon validation of system-on-chIPs using quick error detection
-
Oct
-
D. Lin et al., "Effective Post-Silicon Validation of System-on-ChIPs Using Quick Error Detection," IEEE Trans. Comput.-Aided Des. Integr. Circuits and Syst., vol. 33, no. 10, Oct. 2014.
-
(2014)
IEEE Trans. Comput.-Aided Des. Integr. Circuits and Syst
, vol.33
, Issue.10
-
-
Lin, D.1
-
25
-
-
79959354605
-
Neutron-and proton-induced single event upsets for d-and dice-flIP/flop designs at a 40 nm technology node
-
June
-
T. D. Loveless, et al., "Neutron-and Proton-Induced Single Event Upsets for D-and DICE-FlIP/Flop Designs at a 40 nm Technology Node," IEEE Trans. Nucli. Sci., vol. 58, no.3, June 2011.
-
(2011)
IEEE Trans. Nucli. Sci
, vol.58
, Issue.3
-
-
Loveless, T.D.1
-
26
-
-
80052017953
-
AVF analysis acceleration via hierarchical fault pruning
-
M. Maniatakos et al., "AVF Analysis Acceleration via Hierarchical Fault Pruning," Proc. European Test Symposium, 2011.
-
(2011)
Proc. European Test Symposium
-
-
Maniatakos, M.1
-
27
-
-
79961077712
-
Instruction-level impact analysis of low-level faults in a modern microprocessor controller
-
Sept
-
M. Maniatakos et al., "Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller," IEEE Trans. Computers, vol. 60, no. 9, Sept. 2011.
-
(2011)
IEEE Trans. Computers
, vol.60
, Issue.9
-
-
Maniatakos, M.1
-
29
-
-
41349091201
-
Argus: Low-cost, comprehensive error detection in simple cores
-
A. Meixner, M. E. Bauer, and D. J. Sorin, "Argus: Low-Cost, Comprehensive Error Detection in Simple Cores," Proc. Intl. Symp. Microarchitecture, 2007.
-
(2007)
Proc. Intl. Symp. Microarchitecture
-
-
Meixner, A.1
Bauer, M.E.2
Sorin, D.J.3
-
31
-
-
15044363155
-
Robust system design with built-in soft error resilience
-
Feb
-
S. Mitra et al., "Robust System Design with Built-In Soft Error Resilience," IEEE Computer, vol. 38, no. 2, Feb. 2005
-
(2005)
IEEE Computer
, vol.38
, Issue.2
-
-
Mitra, S.1
-
32
-
-
77953111628
-
Cross-layer resilience challenges: Metrics and optimization
-
S. Mitra, K. Brelsford, and P. N. Sanda, "Cross-Layer Resilience Challenges: Metrics and Optimization," Proc. Design, Automation and Test in Europe, 2010.
-
(2010)
Proc. Design, Automation and Test in Europe
-
-
Mitra, S.1
Brelsford, K.2
Sanda, P.N.3
-
35
-
-
85013779422
-
Architecture design for soft errors
-
S. S. Mukherjee, "Architecture Design for Soft Errors," Morgan Kaufmann, 2008.
-
(2008)
Morgan Kaufmann
-
-
Mukherjee, S.S.1
-
36
-
-
34249825146
-
ReViveI/o: Efficient handling of io in highly-available rollback-recovery servers
-
J. Nakano et al., "ReViveI/O: Efficient Handling of IO in Highly-Available Rollback-Recovery Servers," Proc. Intl. Symp. High-Performance Computer Architecture, 2006.
-
(2006)
Proc. Intl. Symp. High-Performance Computer Architecture
-
-
Nakano, J.1
-
37
-
-
0036507790
-
Error detection by duplicated instructions in super-scalar processors
-
Mar
-
N. Oh, P. P. Shirvani, and E. J. McCluskey, "Error Detection by Duplicated Instructions in Super-Scalar Processors," IEEE. Trans. Reliability, vol. 51, no. 1, Mar. 2002.
-
(2002)
IEEE. Trans. Reliability
, vol.51
, Issue.1
-
-
Oh, N.1
Shirvani, P.P.2
McCluskey, E.J.3
-
38
-
-
77952376526
-
Technologies to further reduce soft error susceptibility in SOI
-
P. Oldiges et al., "Technologies to further reduce soft error susceptibility in SOI," Proc. IEEE Intl. Electron Devices Meeting, 2009.
-
(2009)
Proc. IEEE Intl. Electron Devices Meeting
-
-
Oldiges, P.1
-
39
-
-
84944082078
-
-
OpenSPARC: World's First Free 64-bit Microprocessor
-
"OpenSPARC: World's First Free 64-bit Microprocessor," http://www.opensparc.net.
-
-
-
-
40
-
-
84879304861
-
Fault simulation and emulation tools to augment radiation-hardness assurance testing
-
June
-
H. M. Quinn et al., "Fault Simulation and Emulation Tools to Augment Radiation-Hardness Assurance Testing," IEEE Trans. Nucl. Sci., vol. 60, no. 3, June 2013.
-
(2013)
IEEE Trans. Nucl. Sci
, vol.60
, Issue.3
-
-
Quinn, H.M.1
-
42
-
-
45749133027
-
Soft-error resilience of the IBM POWER6 processor
-
May
-
P. N. Sanda et al., "Soft-error resilience of the IBM POWER6 processor," IBM Journal of Research and Development, vol. 52, no. 3, May 2008.
-
(2008)
IBM Journal of Research and Development
, vol.52
, Issue.3
-
-
Sanda, P.N.1
-
44
-
-
78650044288
-
Radiation-induced soft errors: A chIP-level modeling perspective
-
Feb
-
N. Seifert, "Radiation-induced Soft Errors: A ChIP-level Modeling Perspective," Foundat. Trends® in Electron. Design Autom., vol. 4, no. 2-3, Feb. 2010.
-
(2010)
Foundat. Trends® in Electron. Design Autom
, vol.4
, Issue.2-3
-
-
Seifert, N.1
-
45
-
-
84871392447
-
Soft error susceptibilities of 22 nm tri-gate devices
-
Dec
-
N. Seifert et al., "Soft Error Susceptibilities of 22 nm Tri-Gate Devices," IEEE Trans. Nucl. Sci., vol. 59, no. 6, Dec. 2012.
-
(2012)
IEEE Trans. Nucl. Sci
, vol.59
, Issue.6
-
-
Seifert, N.1
-
46
-
-
84944082080
-
-
Windriver Simics Full System Simulation
-
"Windriver Simics Full System Simulation," http://www.windriver.com/products/simics/.
-
-
-
-
48
-
-
4544282186
-
Characterizing the effects of transient faults on a high-performance processor pIPeline
-
N. J. Wang et al., "Characterizing the Effects of Transient Faults on a High-Performance Processor PIPeline," Proc. Intl. Conf. Dependable Systems and Networks, 2004.
-
(2004)
Proc. Intl. Conf. Dependable Systems and Networks
-
-
Wang, N.J.1
-
50
-
-
0029179077
-
The splash-2 programs: Characterization and methodological considerations
-
S. C. Woo et al., "The SPLASH-2 Programs: Characterization and Methodological Considerations," Proc. Intl. Symp. Computer Architecture, 1995.
-
(1995)
Proc. Intl. Symp. Computer Architecture
-
-
Woo, S.C.1
|