Characterizing the effects of transient faults on a high-performance processor pipeline

Proceedings of the International Conference on Dependable Systems and Networks

Volumn , Issue , 2004, Pages 61-70

  Wang, Nicholas J ^a   Quek, Justin ^a   Rafacz, Todd M ^a   Patel, Sanjay J ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COMPUTER SOFTWARE; CONVERGENCE OF NUMERICAL METHODS; ERROR CORRECTION; LITHOGRAPHY; MATHEMATICAL MODELS; RANDOM ACCESS STORAGE; REDUNDANCY; SCHEDULING;

BRANCH PREDICTION; MICROARCHITECTURES; SCHEDULER; TRANSIENT FAULTS;

MICROPROCESSOR CHIPS;

EID: 4544282186     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dsn.2004.1311877     Document Type: Conference Paper

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