Error detection by duplicated instructions in super-scalar processors

IEEE Transactions on Reliability

Volumn 51, Issue 1, 2002, Pages 63-75

  Oh, Nahmsuk ^a,b   Shirvani, Philip P ^a,b   McCluskey, Edward J ^a,b  

^a IEEE   (United States)

^b Stanford University   (United States)

Author keywords

Concurrent error detection; Error detection by duplicated instructions; Fault tolerance; Fault injection experiment; Instruction level parallelism; Single event upset; Super scalar processor and instruction scheduling; Transient fault

Indexed keywords

DUPLICATED INSTRUCTION; SUPER SCALAR PROCESSORS; TRANSIENT FAULT;

COMPUTER SIMULATION; ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; PROBABILITY; PROGRAM PROCESSORS; STATISTICAL METHODS;

RELIABILITY;

EID: 0036507790     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/24.994913     Document Type: Article

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