A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2012, Pages 153-161

  Asaad, Sameh ^a   Bellofatto, Ralph ^a   Brezzo, Bernard ^a   Haymes, Chuck ^a   Kapur, Mohit ^a   Parker, Benjamin ^a   Roewer, Thomas ^a   Saha, Proshanta ^a   Takken, Todd ^a   Tierno, José ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

FPGA based acceleration; logic emulation; multi core

Indexed keywords

CYCLE ACCURATE; DEBUGGING SUPPORT; DESIGN CYCLE; LOGIC EMULATION; LOGIC LEVELS; LOGIC VERIFICATION; MULTI CORE; MULTI-CORE PROCESSOR; MULTI-FPGA SYSTEM; MULTI-PROCESSOR SOC; PERFORMANCE VALIDATION; PROCESSOR CLOCK SPEED; REPRODUCIBILITIES; SIMULATION SPEED; SOFTWARE SIMULATION; SOFTWARE-BASED; SOI CMOS; SYSTEM DESIGN COMPLEXITY;

CLOCKS; CMOS INTEGRATED CIRCUITS; COMPUTER SOFTWARE; DESIGN; MICROPROCESSOR CHIPS; SYSTEMS ANALYSIS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84858199036     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2145694.2145720     Document Type: Conference Paper

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