A 1.3GHz fifth generation SPARC64 microprocessor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages 245-247+491

  Ando, Hisashige ^a   Yoshida, Yuuji ^a   Inoue, Aiichiro ^a   Sugiyama, Itsumi ^a   Asakawa, Takeo ^a   Morita, Kuniki ^a   Muta, Toshiyuki ^a   Motokurumada, Tsuyoshi ^a   Okada, Seishi ^a   Yamashita, Hideo ^a   Satsukawa, Yoshihiko ^a   Konmoto, Akihiko ^a   Yamashita, Ryouichi ^a   Sugiyama, Hiroyuki ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; COPPER; ERROR CORRECTION; ERROR DETECTION; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; METALLIZING; PHASE LOCKED LOOPS;

BRANCH TARGET ADDRESS CACHE; SPARC64 MICROPROCESSOR;

MICROPROCESSOR CHIPS;

EID: 0038001279     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. A. Inoue, "Fujitsu's New SPARC64 V for Mission-Critical Servers," Microprocessor Forum 2002, Oct. 2002.
2. A. Inoue, "SPARC64 V for Unix Servers" (written in Japanese), Fujitsu, vol. 53.6, Nov. 2002.