-
1
-
-
37549010759
-
Circuit Failure Prediction and Its Application to Transistor Aging
-
Agarwal, M., et al., "Circuit Failure Prediction and Its Application to Transistor Aging," Proc. IEEE VLSI Test Symp., pp. 277-286, 2007.
-
(2007)
Proc. IEEE VLSI Test Symp.
, pp. 277-286
-
-
Agarwal, M.1
-
2
-
-
10744221866
-
A 1.3-GHz Fifth-Generation SPARC64 Microprocessor
-
Nov.
-
Ando, H., et al., "A 1.3-GHz Fifth-Generation SPARC64 Microprocessor", IEEE Journal Solid-State Circuits, Vol. 38, Issue 11, pp. 1896-1905, Nov. 2003.
-
(2003)
IEEE Journal Solid-State Circuits
, vol.38
, Issue.11
, pp. 1896-1905
-
-
Ando, H.1
-
3
-
-
58149267845
-
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance
-
Jan.
-
Bowman, K., et al., "Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance," IEEE Journal Solid-State Circuits, Vol. 44, Issue 1, pp. 49-63, Jan. 2009.
-
(2009)
IEEE Journal Solid-State Circuits
, vol.44
, Issue.1
, pp. 49-63
-
-
Bowman, K.1
-
5
-
-
33846118079
-
Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation
-
Nov.-Dec.
-
Borkar, S.Y., "Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation," IEEE Micro, pp. 10-16, Nov.-Dec. 2005.
-
(2005)
IEEE Micro
, pp. 10-16
-
-
Borkar, S.Y.1
-
6
-
-
0030375853
-
Upset hardened memory design for submicron CMOS technology
-
Calin, T., M. Nicolaidis, and R. Velaco, "Upset Hardened Memory Design for Submicron CMOS Technology," IEEE Trans. Nucl. Sci., Vol. 43, No. 12, pp. 2874-2878, Dec. 1996. (Pubitemid 126770944)
-
(1996)
IEEE Transactions on Nuclear Science
, vol.43
, Issue.6 PART 1
, pp. 2874-2878
-
-
Calin, T.1
Nicolaidis, M.2
Velazco, R.3
-
8
-
-
77953106930
-
Vision for Cross-Layer Optimization to Address the Dual Challenges of Energy and Reliability
-
DeHon, A., et al., "Vision for Cross-Layer Optimization to Address the Dual Challenges of Energy and Reliability," Proc. Design Automation and Test in Europe, 2010.
-
Proc. Design Automation and Test in Europe, 2010
-
-
DeHon, A.1
-
9
-
-
84944408150
-
Razor: A Low-Power Pipeline based on Circuit-level Timing Speculation
-
Ernst, D., et al., "Razor: A Low-Power Pipeline based on Circuit-level Timing Speculation," Proc. IEEE Intl. Symp. Microarchitecture, pp. 7-18, 2003.
-
(2003)
Proc. IEEE Intl. Symp. Microarchitecture
, pp. 7-18
-
-
Ernst, D.1
-
11
-
-
0031388396
-
DEPEND: A Simulation-Based Environment for System Level Dependability Analysis
-
Jan.
-
Goswami, K.K., R.K. Iyer L. Young, "DEPEND: A Simulation-Based Environment for System Level Dependability Analysis," IEEE Trans. Computers, Vol. 46, pp. 60-74, Jan. 1997.
-
(1997)
IEEE Trans. Computers
, vol.46
, pp. 60-74
-
-
Goswami, K.K.1
Iyer, R.K.2
Young, L.3
-
12
-
-
0021439162
-
Algorithm Based Fault Tolerance for Matrix Operations
-
June
-
Huang, K.H., and J.A. Abraham, "Algorithm Based Fault Tolerance for Matrix Operations," IEEE Trans. Computers, Vol. C-33, No. 6, pp. 518-528, June 1984.
-
(1984)
IEEE Trans. Computers
, vol.C-33
, Issue.6
, pp. 518-528
-
-
Huang, K.H.1
Abraham, J.A.2
-
15
-
-
77957911501
-
LEAP: Layout Design through Error-Aware Placement for Soft-Error Resilient Sequential Cell Design
-
Lee, H., et al., "LEAP: Layout Design through Error-Aware Placement for Soft-Error Resilient Sequential Cell Design," Proc. IEEE Intl. Reliability Physics Symp., 2010.
-
Proc. IEEE Intl. Reliability Physics Symp., 2010
-
-
Lee, H.1
-
16
-
-
77953110390
-
ERSA: Error Resilient System Architecture for Probabilistic Applications
-
Leem, L., et al., "ERSA: Error Resilient System Architecture for Probabilistic Applications," Proc. Design Automation and Test in Europe, 2010.
-
Proc. Design Automation and Test in Europe, 2010
-
-
Leem, L.1
-
17
-
-
49749112001
-
CASP: Concurrent Autonomous Chip Self-Test using Stored Test Patterns
-
Li, Y., S. Makar and S. Mitra, "CASP: Concurrent Autonomous Chip Self-Test using Stored Test Patterns," Proc. Design Automation and Test in Europe, pp. 885-890, 2008.
-
(2008)
Proc. Design Automation and Test in Europe
, pp. 885-890
-
-
Li, Y.1
Makar, S.2
Mitra, S.3
-
18
-
-
73249117434
-
Overcoming Early-Life Failure and Aging for Robust Systems
-
Nov.-Dec.
-
Li, Y., et al., "Overcoming Early-Life Failure and Aging for Robust Systems," IEEE Design and Test of Computers, Nov.-Dec. 2009.
-
(2009)
IEEE Design and Test of Computers
-
-
Li, Y.1
-
21
-
-
0025452308
-
Design Techniques for Testable Embedded Error Checkers
-
July
-
McCluskey, E.J., "Design Techniques for Testable Embedded Error Checkers," IEEE Computer, Vol. 23, No. 7, pp. 84-88, July 1990.
-
(1990)
IEEE Computer
, vol.23
, Issue.7
, pp. 84-88
-
-
McCluskey, E.J.1
-
22
-
-
29344456746
-
IBM z990 soft error detection and recovery
-
DOI 10.1109/TDMR.2005.859577
-
Meaney, P., et al., "IBM Z990 Soft Error Detection and Recovery," IEEE Trans. Device and Materials Reliability, Vol. 5, Issue 3, pp. 419-427, Sept. 2005. (Pubitemid 43003061)
-
(2005)
IEEE Transactions on Device and Materials Reliability
, vol.5
, Issue.3
, pp. 419-427
-
-
Meaney, P.J.1
Swaney, S.B.2
Sanda, P.N.3
Spainhower, L.4
-
24
-
-
0034476298
-
Which Concurrent Error Detection Schemes to Choose?
-
Mitra, S., and E.J. McCluskey, "Which Concurrent Error Detection Schemes to Choose?" Proc. IEEE Intl. Test Conf., pp. 985-994, 2000.
-
(2000)
Proc. IEEE Intl. Test Conf.
, pp. 985-994
-
-
Mitra, S.1
McCluskey, E.J.2
-
25
-
-
15044363155
-
Robust System Design with Built-In Soft Error Resilience
-
Feb.
-
Mitra, S., et al., "Robust System Design with Built-In Soft Error Resilience," IEEE Computer, Vol. 38, pp. 43-52, Feb. 2005.
-
(2005)
IEEE Computer
, vol.38
, pp. 43-52
-
-
Mitra, S.1
-
26
-
-
49749121091
-
Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges
-
Mitra, S., "Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges," Proc. Design Automation and Test in Europe, 2008.
-
Proc. Design Automation and Test in Europe, 2008
-
-
Mitra, S.1
-
30
-
-
0036507790
-
Error Detection by Duplicated Instructions in Super-Scalar Processors
-
March
-
Oh, N., P.P. Shirvani and E.J. McCluskey, "Error Detection by Duplicated Instructions in Super-Scalar Processors," IEEE Trans. Reliability, Vol. 51, Issue 1, pp. 63-75, March 2002.
-
(2002)
IEEE Trans. Reliability
, vol.51
, Issue.1
, pp. 63-75
-
-
Oh, N.1
Shirvani, P.P.2
McCluskey, E.J.3
-
31
-
-
0036472442
-
4I: Error detection by diverse data and duplicated instructions
-
DOI 10.1109/12.980007
-
Oh, N., S. Mitra and E.J. McCluskey, "ED4I: Error Detection by Diverse Data and Duplicated Instructions" IEEE Trans. Computers, Vol. 51, No. 2, pp. 180-199, Feb. 2002. (Pubitemid 34198185)
-
(2002)
IEEE Transactions on Computers
, vol.51
, Issue.2
, pp. 180-199
-
-
Oh, N.1
Mitra, S.2
McCluskey, E.J.3
-
32
-
-
46749109635
-
Automated Derivation of Application-Aware Error Detectors using Static Analysis
-
Pattabiraman, K., et. al., "Automated Derivation of Application-Aware Error Detectors using Static Analysis," Proc. IEEE Intl. Symp. On-line Testing, pp. 211-216, 2007.
-
(2007)
Proc. IEEE Intl. Symp. On-line Testing
, pp. 211-216
-
-
Pattabiraman, K.1
-
33
-
-
45749133027
-
Soft Error Resilience of the IBM POWER6 Processor
-
Sanda, P.N., et al., "Soft Error Resilience of the IBM POWER6 Processor," IBM Journal Research and Development, Vol 52, Number 3, 2008.
-
(2008)
IBM Journal Research and Development
, vol.52
, Issue.3
-
-
Sanda, P.N.1
-
34
-
-
0033314330
-
S/390 Parallel Enterprise Server G5 Fault Tolerance
-
Sept./Nov.
-
Spainhower, L., and T.A. Gregg, "S/390 Parallel Enterprise Server G5 Fault Tolerance," IBM Journal Res. and Dev., Vol. 43, pp. 863-873, Sept./Nov., 1999.
-
(1999)
IBM Journal Res. and Dev.
, vol.43
, pp. 863-873
-
-
Spainhower, L.1
Gregg, T.A.2
-
35
-
-
34548308773
-
Verification-guided soft error resilience
-
DOI 10.1109/DATE.2007.364501, 4212011, Proceedings - 2007 Design, Automation and Test in Europe Conference and Exhibition, DATE 2007
-
Seshia, S., W. Li and S. Mitra, "Verification Guided Soft Error Resilience," Proc. Design Automation and Test in Europe, pp. 1442-1447, 2007. (Pubitemid 47334164)
-
(2007)
Proceedings -Design, Automation and Test in Europe, DATE
, pp. 1442-1447
-
-
Seshia, S.A.1
Wenchao, L.2
Mitra, S.3
-
37
-
-
34548303547
-
Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application
-
Singhee, A., and R. A. Rutenbar, "Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application," Proc. Design Automation and Test in Europe, pp. 1379-1384, 2007.
-
(2007)
Proc. Design Automation and Test in Europe
, pp. 1379-1384
-
-
Singhee, A.1
Rutenbar, R.A.2
-
38
-
-
33846595665
-
Sequential element design with built-in soft error resilience
-
DOI 10.1109/TVLSI.2006.887832
-
Zhang, M., et al., "Sequential Element Design with Built-In Soft Error Resilience," IEEE Trans. VLSI, Vol. 14, Issue 12, pp. 1368-1378, Dec. 2006. (Pubitemid 46181213)
-
(2006)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.14
, Issue.12
, pp. 1368-1376
-
-
Zhang, M.1
Mitra, S.2
Mak, T.M.3
Seifert, N.4
Wang, N.J.5
Shi, Q.6
Kim, K.S.7
Shanbhag, N.R.8
Patel, S.J.9
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