Hierarchical simulation approach to accurate fault modeling for system dependability evaluation

IEEE Transactions on Software Engineering

Volumn 25, Issue 5, 1999, Pages 619-632

  Kalbarczyk, Zbigniew ^a,b,c,f   Iyer, Ravishankar K ^a,b,e   Ries, Gregory L ^a   Patel, Jaqdish U ^a,d   Lee, Myeong S ^b,d   Xiao, Yuxiao ^a,b  

^a IEEE

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^c ATI Research Silicon Valley   (United States)

^d CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

^e HEWLETT PACKARD COMPANY   (United States)

^f MicroStrategy   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COMPUTER SYSTEM RECOVERY; DATA STORAGE EQUIPMENT; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; RESPONSE TIME (COMPUTER SYSTEMS);

FAULT DICTIONARIES; HIERARCHICAL SIMULATION;

COMPUTER SYSTEMS PROGRAMMING;

EID: 0033316552     PISSN: 00985589     EISSN: None     Source Type: Journal    
DOI: 10.1109/32.815322     Document Type: Article

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