Instruction-level impact analysis of low-level faults in a modern microprocessor controller

IEEE Transactions on Computers

Volumn 60, Issue 9, 2011, Pages 1260-1273

  Maniatakos, Michail ^a   Karimi, Naghmeh ^b   Tirumurti, Chandra ^c   Jas, Abhijit ^c   Makris, Yiorgos ^d  

^a Yale University   (United States)

^b USA   (United States)

^c INTEL CORPORATION   (United States)

^d The University of Texas at Dallas   (United States)

Author keywords

concurrent error detection; Fault simulation; instruction level error; microprocessor controller

Indexed keywords

CONCURRENT ERROR DETECTION; CONTROL LOGIC; ERROR TYPES; FAULT INJECTION; FAULT SIMULATION; IMPACT ANALYSIS; IN-CONTROL; INSTRUCTION-LEVEL; MICROPROCESSOR CONTROLLER; MODERN MICROPROCESSOR; ONLINE-TESTABILITY; OUT OF ORDER; REGISTER TRANSFER; STUCK-AT FAULTS; SUPERSCALAR; TEST VEHICLE; TRANSIENT ERRORS;

CONCURRENCY CONTROL; CONTROLLERS; CONVOLUTIONAL CODES; ERRORS; MICROPROCESSOR CHIPS;

EMBEDDED SYSTEMS;

EID: 79961077712     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2010.60     Document Type: Article

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