Single-event performance and layout optimization of flip-flops in a 28-nm bulk technology

IEEE Transactions on Nuclear Science

Volumn 60, Issue 4, 2013, Pages 2782-2788

  Lilja, K ^a   Bounasser, M ^a   Wen, S J ^b   Wong, R ^b   Holst, J ^b   Gaspard, N ^c   Jagannathan, S ^c   Loveless, D ^c   Bhuva, B ^c  

^a Robust Chip Inc   (United States)

^b CISCO SYSTEMS   (United States)

^c VANDERBILT UNIVERSITY   (United States)

Author keywords

Dual interlocked cell (DICE); Layout design through Error Aware Positioning (LEAP); radhard design methodology; radiation hardening; radiation hardening by design; single event effect; single event upsets (SEU); soft error

Indexed keywords

DESIGN METHODOLOGY; DUAL-INTERLOCKED CELL (DICE); LAYOUT DESIGNS; RADIATION HARDENING BY DESIGN; SINGLE EVENT EFFECTS; SINGLE EVENT UPSETS; SOFT ERROR;

CMOS INTEGRATED CIRCUITS; RADIATION HARDENING;

DESIGN;

EID: 84883132873     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2013.2273437     Document Type: Article

References (14)

1. O. A. Amusan, L. W. Massengill, M. P. Baze, A. L. Sternberg, A. F. Witulski, B. L. Bhuva, and J. D. Black, "Single-event upsets in deep submicrometer technologies due to charge sharing," IEEE Trans. De vice Mater. Reliab., vol. 8, no. 3, pp. 582-589, Sep. 2008.
2. T. D. Loveless, S. Jagannathan, T. Reece, J. Chetia, B. L. Bhuva, M. W. McCurdy, L. W. Massengill, S.-J. Wen, R. Wong, and D. Rennie, "Neutron and proton-induced single-event upsets for D-and DICE-flip/flop designs at a 40 nm technology node," IEEE Trans. Nucl. Sci., vol. 58, no. 3, pp. 1008-1014, Jun. 2011.
3. N. Seifert, P. Slankard, M. Kirsch, B. Narasimham, V. Zia, C. Brookreson, A. Vo, S. Mitra, B. Gill, and J. Maiz, "Radiation-induced soft error rates of advanced CMOS bulk devices," in Proc. IEEE Intl. Rel. Phys. Symp., 2006, pp. 215-225.
4. J. E. Knudsen and L. T. Clark, "An area and power efficient radiation hardened by design flip-flop," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3392-3399, Dec. 2006. (Pubitemid 46113339)
5. Robust Chip Inc., "Layout Method for Soft-Error Hard Electronics, and Radiation Hardened Logic Cell," USA US12/354, 655, 2008, patent pending.
6. Robust Chip Inc., "Soft-Error Hard Electronic Circuit and Layout," USA US12/763, 139, 2009, patent pending.
7. T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, no. 6, pp. 2874-2878, Dec. 1996. (Pubitemid 126770944)
8. P. Marshall, M. Carts, S. Currie, R. Reed, B. Randall, K. Fritz, K. Kennedy, M. Berg, R. Krithivasan, C. Siedleck, R. Ladbury, C. Marshall, J. Cressler, N. Guofu, K. LaBel, and B. Gilbert, "Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self test (CREST)," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2446-2454, Dec. 2005. (Pubitemid 43269624)
9. B. Bhuva, B. Narasimham, A. Oates, K. Patterson, N. Tam, M. Vilchis, S. Wen, R. Wong, and Y. Xu, "Soft error testing at advanced technology nodes," in IEEE Proc. Intl. Reliability Phys. Symp., 2011, pp. 5B.1.1-5B.1.4.
10. S. Jagannathan, T. D. Loveless, Z. Diggins, B. L. Bhuva, S. J. Wen, R. Wong, and L. W. Massengill, "Neutron-and alpha-particle induced soft-error rates for flip flops at a 40 nm technology node," in IEEE Proc. Intl. Reliability Physics Symp., 2011, pp. SE.5.1-SE.5.5.
11. N. Seifert et al., "On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies," in IEEE Proc. Intl. Reliability Physics Symp., 2010, pp. 188-197.
12. M. P. Baze, M. P. Baze, B. Hughlock, J. Wert, J. Tostenrude, L. Mas-sengill, O. Amusan, R. Lacoe, K. Lilja, and M. Johnson, "Angular dependence of single-event sensitivity in hardened flip/flop designs," IEEE Trans. Nucl. Sci., vol. 55, no. 6, pp. 3295-3301, Dec. 2008.
13. K. Lee, K. Lilja, M. Bounasser, P. Relangi, I. R. Linscott, U. Inan, and S. Mitra, "LEAP: Layout design through error-aware transistor positioning for soft-error resilient sequential cell design," in Proc. IEEE Intl. Rel. Phys. Symp., 2010, pp. 203-412.
14. K. Warren, A. Stenberg, J. Black, R. Weller, R. Reed, M. Mendenhall, R. Schrimpf, and L. Massengill, "Heavy ion testing and single-event upset rate prediction considerations for a DICE flip-flop," IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp. 3130-3137, Dec. 2009.