-
1
-
-
0141761518
-
Tri-gate fully-depleted CMOS transistors: Fabrication, design and layout
-
B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, "Tri-gate fully-depleted CMOS transistors: Fabrication, design and layout, " in Proc. IEEE Symp. VLSI Technol. Dig. Tech. Papers, 2003, pp. 133-134.
-
(2003)
Proc. IEEE Symp. VLSI Technol. Dig. Tech. Papers
, pp. 133-134
-
-
Doyle, B.1
Boyanov, B.2
Datta, S.3
Doczy, M.4
Hareland, S.5
Jin, B.6
Kavalieros, J.7
Linton, T.8
Rios, R.9
Chau, R.10
-
2
-
-
41149171855
-
Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering
-
1705211, 2006 Symposium on VLSI Technology, VLSIT - Digest of Technical Papers
-
J. Kavalieros, B. Doyle, S. Datta, G. Dewey, M. Doczy, B. Jin, D. Lionberger, M. Metz, W. Rachmady, M. Radosavljevic, U. Shah, N. Zelick, and R. Chau, "Tri-gate transistor architecture with high-k gate dielectrics, metal gates and strain engineering, " in Proc. IEEE Symp. VLSI Technol. Dig. Tech. Papers, 2006, pp. 50-51. (Pubitemid 351424120)
-
(2006)
Digest of Technical Papers - Symposium on VLSI Technology
, pp. 50-51
-
-
Kavalieros, J.1
Doyle, B.2
Datta, S.3
Dewey, G.4
Doczy, M.5
Jin, B.6
Lionberger, D.7
Metz, M.8
Rachmady, W.9
Radosavljevic, M.10
Shah, U.11
Zelick, N.12
Chau, R.13
-
3
-
-
83855161646
-
Laser-and heavy ion-induced charge collection in bulk finFETs
-
Dec.
-
F. El-Mamouni, E. X. Zhang, N. D. Pate, R. D. Schrimpf, R. A. Reed, K. F. Galloway, D. McMorrow, J. Warner, E. Simoen, C. Claeys, A. Griffoni, D. Linten, and G. Vizkelethy, "Laser-and heavy ion-induced charge collection in bulk finFETs, " IEEE Trans. Nucl. Sci., vol. 58, no. 6, pp. 2563-2569, Dec. 2011.
-
(2011)
IEEE Trans. Nucl. Sci
, vol.58
, Issue.6
, pp. 2563-2569
-
-
El-Mamouni, F.1
Zhang, E.X.2
Pate, N.D.3
Schrimpf, R.D.4
Reed, R.A.5
Galloway, K.F.6
McMorrow, D.7
Warner, J.8
Simoen, E.9
Claeys, C.10
Griffoni, A.11
Linten, D.12
Vizkelethy, G.13
-
4
-
-
83255166535
-
Neutron-induced charge collection simulation of bulk finFET SRAMs compared with conventional planar SRAMs
-
Dec.
-
Y. Fang and A. S. Oates, "Neutron-induced charge collection simulation of bulk finFET SRAMs compared with conventional planar SRAMs, " IEEE Trans. Device Mater. Rel., vol. 11, no. 4, pp. 551-554, Dec. 2011.
-
(2011)
IEEE Trans. Device Mater. Rel
, vol.11
, Issue.4
, pp. 551-554
-
-
Fang, Y.1
Oates, A.S.2
-
5
-
-
77952331615
-
High performance 32 nm logic technology featuring 2nd generation high-k metal gate transistors
-
P. Packan et al., "High performance 32 nm logic technology featuring 2nd generation high-k metal gate transistors, " in Proc. IEEE Int. Electron Devices Meeting Tech. Dig., 2009, pp. 1-4.
-
(2009)
Proc. IEEE Int. Electron Devices Meeting Tech. Dig
, pp. 1-4
-
-
Packan, P.1
-
6
-
-
84866526723
-
A22 nmhigh performance and low-powerCMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
-
C. Auth et al., "A22 nmhigh performance and low-powerCMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors, " in Proc. IEEE Symp. VLSI Technol. Dig. Tech. Papers, 2012, pp. 131-132.
-
(2012)
Proc. IEEE Symp. VLSI Technol. Dig. Tech. Papers
, pp. 131-132
-
-
Auth, C.1
-
8
-
-
0242443635
-
Measurements and analysis of ser tolerant latch in a 90 nm dual-Vt CMOS process
-
P. Hazucha, T. Karnik, S. Walstra, B. Bloechel, J. Tschanz, J. Maiz, K. Soumyanath, G. Dermer, S. Narendra, V. De, and S. Borkar, "Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process, " in Proc. IEEE Custom Integr. Circuits Conf., 2003, pp. 617-620.
-
(2003)
Proc. IEEE Custom Integr. Circuits Conf
, pp. 617-620
-
-
Hazucha, P.1
Karnik, T.2
Walstra, S.3
Bloechel, B.4
Tschanz, J.5
Maiz, J.6
Soumyanath, K.7
Dermer, G.8
Narendra, S.9
De, V.10
Borkar, S.11
-
9
-
-
77957898943
-
On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies
-
N. Seifert, V. Ambrose, B. Gill, Q. Shi, R. Allmon, C. Recchia, S. Mukherjee, N. Nassif, J. Krause, J. Pickholtz, and A. Balasubramanian, "On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies, " in Proc. IEEE Int. Rel. Phys. Symp., 2010, pp. 188-197.
-
(2010)
Proc. IEEE Int. Rel. Phys. Symp
, pp. 188-197
-
-
Seifert, N.1
Ambrose, V.2
Gill, B.3
Shi, Q.4
Allmon, R.5
Recchia, C.6
Mukherjee, S.7
Nassif, N.8
Krause, J.9
Pickholtz, J.10
Balasubramanian, A.11
-
10
-
-
70449106113
-
Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32 nm technology node
-
B. Gill, N. Seifert, and V. Zia, "Comparison of alpha-particle and neutron-induced combinational and sequential logic error rates at the 32 nm technology node, " in Proc. IEEE Int. Rel. Phys. Symp., 2009, pp. 199-205.
-
(2009)
Proc. IEEE Int. Rel. Phys. Symp
, pp. 199-205
-
-
Gill, B.1
Seifert, N.2
Zia, V.3
-
11
-
-
84871378876
-
Real-time soft-error testing results of 45 nm, high-K metal gate, bulk CMOS SRAMs
-
Dec presented at NSREC 2012 submitted for publication
-
N. Seifert andM. Kirsch, "Real-time soft-error testing results of 45 nm, high-K metal gate, bulk CMOS SRAMs, " IEEE Trans. Nucl. Sci., Dec. 2012, presented at NSREC 2012, submitted for publication.
-
(2012)
IEEE Trans. Nucl. Sci.
-
-
Seifert, N.1
Kirsch, M.2
-
12
-
-
51549107392
-
Multi-cell upset probabilities of 45 nm high-k metal gate SRAM devices in terrestrial and space environments
-
N. Seifert, B. Gill, K. Foley, and P. Relangi, "Multi-cell upset probabilities of 45 nm high-k metal gate SRAM devices in terrestrial and space environments, " in Proc. IEEE Int. Rel. Phys. Symp., 2008, pp. 181-186.
-
(2008)
Proc. IEEE Int. Rel. Phys. Symp
, pp. 181-186
-
-
Seifert, N.1
Gill, B.2
Foley, K.3
Relangi, P.4
-
14
-
-
78650044288
-
Radiation-induced soft errors: A chip-level modeling perspective
-
N. Seifert, "Radiation-induced soft errors: A chip-level modeling perspective, " Foundat. Trends® in Electron. Design Autom., vol. 4, no. 2-3, pp. 99-221, 2010.
-
(2010)
Foundat. Trends® in Electron. Design Autom
, vol.4
, Issue.2-3
, pp. 99-221
-
-
Seifert, N.1
-
15
-
-
0036931372
-
Modeling the effect of technology trends on the soft error rate of combinational logic
-
Jun
-
P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi, "Modeling the effect of technology trends on the soft error rate of combinational logic, " in Proc. IEEE Depend. Syst. Netw. Conf., Jun. 2002, pp. 389-398.
-
(2002)
Proc. IEEE Depend. Syst. Netw. Conf.
, pp. 389-398
-
-
Shivakumar, P.1
Kistler, M.2
Keckler, S.W.3
Burger, D.4
Alvisi, L.5
|