Novel low-power and highly reliable radiation hardened memory cell for 65 nm CMOS technology

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 61, Issue 7, 2014, Pages 1994-2001

  Guo, Jing ^a   Xiao, Liyi ^a   Mao, Zhigang ^a  

^a HARBIN INSTITUTE OF TECHNOLOGY   (China)

Author keywords

Critical charge; radiation hardened memory; reliability; single event upsets (SEUs); soft errors

Indexed keywords

CELLS; CMOS INTEGRATED CIRCUITS; CYTOLOGY; HARDENING; MEMORY ARCHITECTURE; RELIABILITY; SEMICONDUCTOR STORAGE; TRANSIENTS;

65 NM CMOS TECHNOLOGIES; CHARGE SHARING; CRITICAL CHARGE; MULTIPLE NODES; RADIATION-HARDENED; SINGLE EVENT UPSETS; SOFT ERROR; STATIC POWER;

RADIATION HARDENING;

EID: 84903721058     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2014.2304658     Document Type: Article

References (32)

1. E. Ibe et al., "Impact of scaling on neutron induced soft error in SRAMsfrom an 250 nm to a 22 nm design rule, " IEEE Trans. Electron Devices, vol. 57, no. 7, pp. 1527-1538, Jul. 2010.
2. S. Martinie et al., "Underground experiment and modeling of alphaemitters induced soft-error rate in CMOS 65 nm SRAM, " IEEE Trans.Nucl. Sci., vol. 59, no. 4, pp. 1048-1053, Aug. 2012.
3. R. C. Baumann, "Soft errors in advanced semiconductor devices-PartI: the three radiation sources, " IEEE Trans. Device Mater. Rel., vol. 1, no. 1, pp. 17-22, Mar. 2001.
4. P. E. Dodd and L.W.Massengill, "Basic mechanisms and modeling ofsingle-event upset in digital microelectronics, " IEEE Trans. Nucl. Sci., vol. 50, no. 3, pp. 583-602, Jun. 2003.
5. H. L. Hughes and J. M. Benedetto, "Radiation effects and hardeningof MOS technology devices and circuits, " IEEE Trans. Nucl. Sci., vol.50, no. 3, pp. 500-521, Jun. 2003.
6. H.-H. K. Lee et al., "LEAP: Layout design through error-awaretransistor positioning for soft-error resilient sequential cell design, " inProc. IRPS, 2010, pp. 203-212.
7. T. Karnik, P. Hazucha, and J. Patel, "Characterization of soft errorscaused by single event upsets in CMOS processes, " IEEE Trans. Depend.Secure Comput., vol. 1, no. 2, pp. 128-143, Apr.-Jun. 2004.
8. [Online]. Available: http://www.cs.sandia.gov/CSRI/Workshops/2008/ FaultTolerantSpaceborne/presentations/Cohn-DTRAFTC.workshop.6.08-public.pdf
9. [Online]. Available: http://nepp.nasa.gov/workshops/etw2010/talks/
10. P. Reviriego, J. A. Maestro, and M. F. Flanagan, "Error detectionin majority logic decoding of euclidean geometry low density paritycheck (EG-LDPC) codes, " IEEE Trans. VLSI Syst., vol. 21, no. 1, pp.156-159, Jan. 2013.
11. C. Argyrides, D. K. Pradhan, and T. Kocak, "Matrix codes for reliableand cost efficient memory chips, " IEEE Trans. VLSI Syst., vol. 19, no.3, pp. 420-428, Mar. 2011.
12. S.-F. Liu, P. Reviriego, and J. A. Maestro, "Efficient majority logicfault detection with difference-set codes for memory applications, "IEEE Trans. VLSI Syst., vol. 20, no. 1, pp. 148-156, Jan. 2012.
13. C.Yang, Y. Emre, and C. Chakrabarti, "Product code schemes for errorcorrection in MLC NAND flash memories, " IEEE Trans. VLSI Syst., vol. 20, no. 12, pp. 2302-2314, Dec. 2012.
14. S. M. Jahinuzzaman, D. J. Rennie, and M. Sachdev, "A soft error tolerant10T SRAMbit-cellwith differential read capability, " IEEE Trans.Nucl. Sci., vol. 56, no. 6, pp. 3768-3773, Dec. 2009.
15. S. Lin, Y.-B. Kim, and F. Lombardi, "A 11-transistor nanoscale CMOSmemory cell for hardening to soft errors, " IEEE Trans. VLSI Syst., vol.19, no. 5, pp. 900-904, May 2012.
16. S. Lin, Y.-B. Kim, and F. Lombardi, "Analysis and design of nanoscaleCMOS storage elements for single-event hardening withmultiple- nodeupset, " IEEE Trans. Device Mater. Rel., vol. 12, no. 1, pp. 17-22, Mar.2012.
17. I.-S. Jung, Y.-B. Kim, and F. Lombardi, "A novel sort error hardened10T SRAM cells for low voltage operation, " in Proc. MWSCAS, 2012, pp. 714-717.
18. T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory designfor submicron CMOS technology, " IEEE Trans. Nucl. Sci., vol.43, no. 6, pp. 2874-2878, Dec. 1996.
19. D. R. Blum and J. G. Delgado-Frias, "Hardened by design techniquesfor implementing multiple-bit upset tolerant static memories, " in Proc.ISCAS, 2007, pp. 2786-2789.
20. J. D. Black, P. E. Dodd, and K. M. Warren, "Physics of multiplenodecharge collection and impacts on single-event characterizationand soft error rate prediction, " IEEE Trans. Nucl. Sci., vol. 60, no. 3, pp. 1836-1850, Jun. 2013.
21. O. A. Amusan et al., "Charge collection and charge sharing in a 130nm CMOS technology, " IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp.3253-3258, Dec. 2006.
22. F. Vargas and M. Nicolaidis, "SEU-tolerant SRAM design based oncurrent monitoring, " in Proc. FTCS-24, 1994, pp. 106-115.
23. C.-Y. Hsieh et al., "Independently-controlled-gate finFET Schmitttrigger sub-threshold SRAMS, " IEEE Trans. VLSI Syst., vol. 20, no.7, pp. 1201-1209, Jul. 2012.
24. M. Nicolaidis, R. Perez, and D. Alexandrescu, "Low-cost highly-robusthardened cells using blocking feedback transistors, " in Proc. VTS, 2008, pp. 371-376.
25. C.-C. Wang et al., "Single-ended SRAM with high test coverageand short test time, " IEEE J. Solid-State Circuits, vol. 35, no. 1, pp.114-118, Jan. 2000.
26. H. Nan and K. Choi, "High performance, low cost, and robust soft errortolerant latch designs for nanoscale CMOS technology, " IEEE Trans.Circuits Syst.-I: Reg. Papers, vol. 59, no. 7, pp. 1445-1457, Jul. 2012.
27. M. Omana, D. Rossi, and C. Metra, "High-performance robustlatches, " IEEE Trans. Comput., vol. 59, no. 11, pp. 1455-1465, Nov.2010.
28. M. Y. Hsiao, D. C. Bossen, and R. T. Chien, "Orthogonal latin squarecodes, " IBM J. Res. Develop., vol. 14, no. 4, pp. 390-394, Jul. 1970.
29. P. Reviriego, S. Pontarelli, and J. A.Maestro, "Concurrent error detectionfor orthogonal latin squares encoders and syndrome computation, "IEEE Trans. VLSI Syst., vol. 21, no. 12, pp. 2334-2338, Dec. 2013.
30. J. Guo et al., "Novel mixed codes for multiple-cell upsets mitigationin static RAMs, " IEEE Micro, vol. 33, no. 6, pp. 66-74, Nov. 2013.
31. S. Liu et al., "Comparison of the susceptibility to soft errors of SRAMbasedFPGA error correction codes implementations, " IEEE Trans.Nucl. Sci., vol. 59, no. 3, pp. 619-624, Jun. 2012.
32. P. Reviriego et al., "Multiple cell upset correction in memories usingdifference set codes, " IEEE Trans. Circuits Syst.-I:Reg. Papers, vol.59, no. 11, pp. 2592-2599, Nov. 2012.