A 11-transistor nanoscale CMOS memory cell for hardening to soft errors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 5, 2011, Pages 900-904

  Lin, Sheng ^a   Kim, Yong Bin ^a   Lombardi, Fabrizio ^a  

^a Northeastern University   (United States)

Author keywords

Memory design; nanotechnology; radiation hardening

Indexed keywords

CMOS MEMORY; CONVENTIONAL MEMORIES; FEATURE SIZES; MEMORY CELL; MEMORY DESIGN; NANOSCALE CMOS; NOVEL ACCESS; POWER DELAY PRODUCT; SIMULATION RESULT; SOFT ERROR; SOFT-ERROR TOLERANCE; TRANSIENT PULSE;

CELLS; DESIGN; ERROR CORRECTION; HARDENING; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; SEMICONDUCTOR STORAGE;

RADIATION HARDENING;

EID: 79955561909     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2043271     Document Type: Article

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