Low-cost highly-robust hardened cells using blocking feedback transistors

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2008, Pages 371-376

  Nicolaidis, Michael ^a   Perez, Renaud ^b   Alexandrescu, Dan ^b  

^a GRENOBLE INSTITUTE OF TECHNOLOGY   (France)

^b iRoC Technologies

Author keywords

[No Author keywords available]

Indexed keywords

STORAGE CELLS; VLSI TESTS;

DATA STORAGE EQUIPMENT; ERROR ANALYSIS; ERROR CORRECTION; FLIP FLOP CIRCUITS; HARDENING; MICROPROCESSOR CHIPS;

CELLS;

EID: 51449114909     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2008.15     Document Type: Conference Paper

References (8)

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3. S. Whitaker, J. Canaris, and K. Liu, "SEU Hardened Memory Cells for a CCSDS Reed Solomon Encoder", IEEE Trans. on Nuclear Sc., vol. NS-38, no 6, Dec 1991, pp. 1471-1477.
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5. M. Omana, D. Rossi, C. Metra, "Novel Transient Fault Hardened Static Latch", Proc 18th International Test Conference, pp. 886-892, 2003.
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7. M. Nicolaidis, "Cellule de mémorisation durcie", French patent application, filed July 5, 2005.
8. M. Nicolaidis, "Mitigation Techniques for Single Event Effects", oral presentation in Special Session: Simulation and Mitigation of Single Event Effects, 2005 IEEE International On-Line Testing Symposium, July 6-8, 2005, St Raphael, France.