A novel sort error hardened 10T SRAM cells for low voltage operation

Midwest Symposium on Circuits and Systems

Volumn , Issue , 2012, Pages 714-717

  Jung, In Seok ^a   Kim, Yong Bin ^a   Lombardi, Fabrizio ^a  

^a Northeastern University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; LOW VOLTAGE OPERATION; SIMULATED RESULTS; SINGLE EVENT TRANSIENTS; SOFT ERROR; SRAM CELL; STANDARD CMOS PROCESS; STATIC NOISE MARGIN; SUBTHRESHOLD;

CMOS INTEGRATED CIRCUITS; HARDENING; THRESHOLD VOLTAGE; TRANSIENTS;

STATIC RANDOM ACCESS STORAGE;

EID: 84867313932     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2012.6292120     Document Type: Conference Paper

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