Comparison of the susceptibility to soft errors of SRAM-Based FPGA error correction codes implementations

IEEE Transactions on Nuclear Science

Volumn 59, Issue 3 PART 2, 2012, Pages 619-624

  Liu, S ^a   Sorrenti, G ^b   Reviriego, P ^a   Casini, F ^b   Maestro, J A ^a   Alderighi, M ^c   Mecha, H ^d  

^a UNIVERSIDAD ANTONIO DE NEBRIJA   (Spain)

^b Sanitas EG Srl   (Italy)

^c Istituto Nazionale d'Astrofisica   (Italy)

^d UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

Author keywords

Decoder; fault injection; field programmable gate array (FPGA); hamming code; one step majority logic decoding; single event upsets

Indexed keywords

CIRCUIT FUNCTIONALITY; CONFIGURATION MEMORY; DECODER; DIFFERENCE-SET CYCLIC; ERROR CORRECTION CODES; FAULT INJECTION; HAMMING CODE; HARSH ENVIRONMENT; MEMORY CELL; SINGLE EVENT UPSETS; SOFT ERROR; SRAM-BASED FPGA;

ELECTRIC NETWORK ANALYSIS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MAJORITY LOGIC; SEMICONDUCTOR STORAGE; SIGNAL RECEIVERS; STATIC RANDOM ACCESS STORAGE;

COMPUTER CONTROL SYSTEMS;

EID: 84862631163     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2012.2193417     Document Type: Article

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