Analysis and design of nanoscale CMOS storage elements for single-event hardening with multiple-node upset

IEEE Transactions on Device and Materials Reliability

Volumn 12, Issue 1, 2012, Pages 68-77

  Lin, Sheng ^a   Kim, Yong Bin ^a   Lombardi, Fabrizio ^a  

^a Northeastern University   (United States)

Author keywords

Memory design; nanotechnology; radiation hardening; soft error (SE)

Indexed keywords

ANALYSIS AND DESIGN; CHARGE SHARING; CRITICAL CHARGE; CURRENT SOURCES; DEVICE SIZES; FEATURE SIZES; LAYOUT AREA; MEMORY CELL; MEMORY DESIGN; MONTE CARLO SIMULATION; NANOSCALE CMOS; NODE PAIRS; POWER SUPPLY VOLTAGE; REALISTIC SCENARIO; SCHMITT TRIGGER; SINGLE EVENT; SINGLE-EVENTS; SOFT ERROR; STORAGE ELEMENTS; TECHNICAL LITERATURE; TEMPERATURE VARIATION; TRANSMISSION GATE;

DESIGN; MONTE CARLO METHODS; NANOTECHNOLOGY; RADIATION HARDENING; SEMICONDUCTOR STORAGE;

HARDENING;

EID: 84863255466     PISSN: 15304388     EISSN: 15582574     Source Type: Journal    
DOI: 10.1109/TDMR.2011.2167233     Document Type: Article

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