Single-ended SRAM with high test coverage and short test time

IEEE Journal of Solid-State Circuits

Volumn 35, Issue 1, 2000, Pages 114-118

  Wang, Chua Chin ^a   Wu, Chi Feng ^a   Hwang, Rain Ted ^a   Kao, Chia Hsiung ^a  

^a NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC LOSSES; MICROPROCESSOR CHIPS; QUALITY CONTROL;

STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0033908206     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.818928     Document Type: Article

References (7)

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2. A. J. van de Goor, Testing Semiconductor Memories. New York: Wiley, 1991.
3. K. M. Wallquist, "On the effect of ISSQ testing in reducing early failure rate," in Proc. Int. Test Conf., 1995, pp. 910-915.
4. A. D. Singh, H. Rasheed, and W. W. Weber, "IDDQ testing of CMOS opens: An experimental study," in Proc. Int. Test Conf., 1995, pp. 479-489.
5. B. Prince, Semiconductor Memories. New York: Wiley, 1996.
6. P. Singer, "New tools for failure analysis," Semiconduct. Int., pp. 78-82, Sept. 1996.
7. J. S. Caravella, "A low voltage SRAM for embedded applications," IEEE J. Solid-State Circuits, vol. 32, pp. 428-432, Mar. 1997.