Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays

Applied Physics Letters

Volumn 103, Issue 26, 2013, Pages

  Clement N ^a   Han, X L ^a   Larrieu, G ^b  

^a INSTITUT D ELECTRONIQUE   (France)

^b UNIVERSITÉ DE TOULOUSE   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC TRANSPORT; ELECTROSTATIC CONTROL; LOW NOISE LEVELS; LOW-FREQUENCY NOISE; PARALLELIZATIONS; SILICON NANOWIRE DEVICE; SILICON NANOWIRE TRANSISTORS; TRANSISTOR OPERATION;

SILICON; THRESHOLD VOLTAGE;

NANOWIRES;

EID: 84891621015     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.4858955     Document Type: Article

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