Realization of a silicon nanowire vertical surround-gate field-effect transistor

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Volumn 2, Issue 1, 2006, Pages 85-88

  Schmidt, Volker ^a,b   Riel, Heike ^a   Senz, Stephan ^b   Karg, Siegfried ^a   Riess, Walter ^a   Gösele, Ulrich ^b  

^a IBM RESEARCH ZURICH   (Switzerland)

^b MAX PLANCK INSTITUTE OF MICROSTRUCTURE PHYSICS   (Germany)

Author keywords

Chemical vapor deposition; Field effect transistors; Nanowires; Silicon

Indexed keywords

CHEMICAL VAPOR DEPOSITION; CURING; EPITAXIAL GROWTH; NANOSTRUCTURED MATERIALS; POLYIMIDES; PROBABILITY; SILICON;

GATE-VOLTAGE-DEPENDENT CURRENT; NANOWIRES; POLYIMIDE CURING; SILICON SUBSTRATE;

FIELD EFFECT TRANSISTORS;

NANOMATERIAL; SILICON;

ARTICLE; CHEMISTRY; CONFORMATION; CRYSTALLIZATION; ELECTRIC CONDUCTIVITY; ELECTROCHEMISTRY; EQUIPMENT; EQUIPMENT DESIGN; EVALUATION; INSTRUMENTATION; MATERIALS TESTING; METHODOLOGY; MICROELECTRODE; NANOTECHNOLOGY; PARTICLE SIZE; SEMICONDUCTOR; SURFACE PROPERTY; ULTRASTRUCTURE;

CRYSTALLIZATION; ELECTRIC CONDUCTIVITY; ELECTROCHEMISTRY; EQUIPMENT DESIGN; EQUIPMENT FAILURE ANALYSIS; MATERIALS TESTING; MICROELECTRODES; MOLECULAR CONFORMATION; NANOSTRUCTURES; NANOTECHNOLOGY; PARTICLE SIZE; SILICON; SURFACE PROPERTIES; TRANSISTORS;

EID: 32044458180     PISSN: 16136810     EISSN: 16136829     Source Type: Journal    
DOI: 10.1002/smll.200500181     Document Type: Article

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