A sub-0.3 v area-efficient l-shaped 7t sram with read bitline swing expansion schemes based on boosted read-bitline, asymmetric-V$ \ TH read-port, and offset cell vdd biasing techniques

IEEE Journal of Solid-State Circuits

Volumn 48, Issue 10, 2013, Pages 2558-2569

  Chang, Meng Fan ^a   Chen, Ming Pin ^a,b   Chen, Lai Fu ^a,b   Yang, Shu Meng ^b   Kuo, Yao Jen ^b   Wu, Jui Jen ^b   Su, Hsiu Yun ^a   Chu, Yuan Hua ^a   Wu, Wen Ching ^a   Yang, Tzu Yi ^a   Yamauchi, Hiroyuki ^c  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^c FUKUOKA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Bit line swing; hot carrier injection; low voltage; read port; SRAM

Indexed keywords

BIASING TECHNIQUES; BIT LINES; HOT CARRIER INJECTION; LOW VOLTAGES; LOW-VOLTAGE APPLICATIONS; OPERATING VOLTAGE; READ-PORT; SENSING MARGIN;

CYTOLOGY; LOGIC DESIGN; STATIC RANDOM ACCESS STORAGE;

CELLS;

EID: 84884821405     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2013.2273835     Document Type: Article

References (40)

1. M. Yamaoka, N. Maeda, Y. Shinozaki, Y. Shimazaki, K. Nii, S. Shimada, K. Yanagisawa, and T. Kawahara, "Low-power embedded SRAM modules with expanded margins for writing," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005, pp. 480-611.
2. K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, "A 3-GHz 70-Mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 146-151, Jan. 2006. (Pubitemid 43145972)
3. H. Pilo, J. Barwin, G. Braceras, C. Browning, S. Burns, J. Gabric, S. Lamphier, M. Miller, A. Roberts, and F. Towler, "An SRAM design in 65 nm and 45 nm technology nodes featuring read and write-assist circuits to expand operating voltage," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2006, pp. 15-16. (Pubitemid 351306250)
4. K. Nii, M. Yabuuchi, Y. Tsukamoto, S. Ohbayashi, S. Imaoka, H. Makino,Y.Yamagami, S. Ishikura,T.Terano, T. Oashi, K.Hashimoto, A. Sebe, G. Okazaki, K. Satomi, H. Akamatsu, and H. Shinohara, "A 45-nm bulk CMOS embedded SRAM with improved immunity against process and temperature variations," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 180-191, Jan. 2008.
5. S. Ohbayashi, M.Yabuuchi,K.Nii,Y. Tsukamoto, S. Imaoka, Y.Oda, T. Yoshihara, M. Igarashi,M. Takeuchi,H. Kawashima, Y.Yamaguchi, K. Tsukamoto, M. Inuishi, H. Makino, K. Ishibashi, and H. Shinohara, "A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits," IEEE J. Solid-State Circuit, vol. 42, no. 4, pp. 820-829, Apr. 2007. (Pubitemid 46495399)
6. K. Sohn, Y.-H. Suh, Y.-J. Son, D.-S. Yim, K.-Y. Kim, D.-G. Bae, T. Kang, H. Lim, S.-M. Jung, H.-G. Byun, Y.-H. Jun, and K. Kim, "A 100 nm double-stacked 500 Mhz 72 Mb separate-I/O synchronous SRAM with automatic cell-bias scheme and adaptive block redundancy," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2008, pp. 386-622.
7. O. Hirabayashi, A. Kawasumi, A. Suzuki, Y. Takeyama, K. Kushida, T. Sasaki, A. Katayama, G. Fukano, Y. Fujimura, T. Nakazato, Y. Shizuki, N. Kushiyama, and T. Yabe, "A process-variation-tolerant dual-power-supply SRAMwith 0.179 cell in 40 nm CMOS using level-programmable wordline driver," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009, pp. 458-459.
8. T. Suzuki, H. Yamauchi, Y. Yamagami, K. Satomi, and H. Akamatsu, "A stable 2-port SRAM cell design against simultaneously read/writedisturbed accesses," IEEE J. Solid-State Circuits, vol. 43, no. 9, pp. 2109-2119, Sep. 2008.
9. Y.Morita, H. Fujiwara, H. Noguchi, and Y. Iguchi, "An area-conscious low-voltage-oriented 8T-SRAM design under DVS environment," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, pp. 256-257. (Pubitemid 351306645)
10. N. Verma and A. P. Chandrakasan, "A 65 nm 8T sub-Vt SRAM employing sense-amplifier redundancy," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 328-606.
11. I. J. Chang, J. J. Kim, S. P. Park, and K. Roy, "A 32 kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90 nm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2008, pp. 388-622.
12. Y. H. Chen, W. M. Chan, S. Y. Chou, H. J. Liao, H. Y. Pan, J. J. Wu, C. H. Lee, S. M. Yang, Y. C. Liu, and H. Yamauchi, "A 0.6 V 45 nm adaptive dual-rail SRAM compiler circuit design for lower VDD-min VLSIs," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2008, pp. 210-211.
13. M. Khellah, N. S. Kim, J. Howard, G. Ruhl, M. Sunna, Y. Ye, J. Tschanz, D. Somasekhar, N. Borkar, F. Hamzaoglu, G. Pandya, A. Farhang, K. Zhang, and V. De, "A 4.2 GHz 0.3 mm 256 Kb dual-V SRAM building block in 65 nm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp. 2572-2581.
14. M. Yamaoka, K. Osada, and K. Ishibashi, "0.4-V logic-library- friendly SRAM array using rectangular-diffusion cell and delta-boosted-array voltage scheme," IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 934-940, Jun. 2004.
15. N. Shibata, H. Kiya, S. Kurita, H. Okamoto, M. Tan'no, and T. Douseki, "A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment-Sure write operation by using step-down negatively overdriven bitline scheme," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 728-742, March 2006.
16. D. P.Wang,H. J. Liao, H. Yamauchi,Y.H. Chen, Y. L. Lin, S. H. Lin, D. C. Liu, H. C. Chang, and W. Hwang, "A 45 nm dual-port SRAM with write and read capability enhancement at low voltage," in Proc. IEEE Int. SOC Conf., Sep. 2007, pp. 211-214.
17. M. Khellah, Y. Ye, N. S. Kim, D. Somasekhar, G. Pandya, A. Farhang, K. Zhang, C. Webb, and V. De, "Wordline & bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65 nm CMOS designs," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2006, pp. 9-10. (Pubitemid 351306247)
18. K. Kushida, K. Kushida, A. Suzuki, G. Fukano, A. Kawasumi, O. Hirabayashi, Y. Takeyama, T. Sasaki, A. Katayama, Y. Fujimura, and T. Yabe, "A 0.7 V single-supply SRAM with 0.495 cell in 65 nm Technology utilizing self-write-back sense amplifier and cascaded bit line scheme," IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1192-1198, Apr. 2009.
19. K. Nii et al., "A 0.5 V 100 MHz PD-SOI with enhanced read stability and write margin by asymmetric MOSFET and forward body bias," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2010, pp. 356-357, (halo).
20. M. Suzuki et al., "Post-fabrication self-convergence scheme for suppressing variability inSRAM cells and logic transistors," in Symp. VLSI Technology Dig. Tech. Papers, Jun. 2009, pp. 148-149.
21. K. Miyaji et al., "Improvement of read margin and its distribution by Vth mismatch self-repair in 6T-SRAM with asymmetric pass gate transistor formed by post-process local electron injection," IEEE J. Solid-State Circuits, vol. 46, no. 9, pp. 2180-2188, Sep. 2011.
22. M.-F. Chang et al., "Endurance-aware circuit designs of nonvolatile logic and nonvolatile SRAM using resistive memory (Memristor) device," in Proc. 2012 IEEE Asia South Pacific Design Automation Conf. (ASP-DAC), Jan. 2012, pp. 329-334.
23. K. Takeda et al., "A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 113-121, Jan. 2006. (Pubitemid 43145968)
24. L. Chang et al., "Stable SRAM Cell Design for the 32 nm Node and Beyond," in Symp. VLSI Technology. Dig. Tech. Papers, Jun. 2005, pp. 128-129. (Pubitemid 43897595)
25. S. Ishikura et al., "A 45 nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, pp. 254-255. (Pubitemid 351306644)
26. R. Joshi et al., " low Vmin, read and half select disturb-free 1.2 Mb SRAM," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2007, pp. 250-251. (Pubitemid 351306642)
27. L. Chang et al., "An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 956-963, Apr. 2008.
28. T.-H. Kim, J. Liu, and C. H. Kim, "A voltage scalable 0.26 V, 64 kb 8T SRAM with Vmin lowering techniques and deep sleep mode," IEEE J. Solid-State Circuits, vol. 44, no. 6, pp. 1785-1795, 2009.
29. J.-J. Wu, Y.-H. Chen, M.-F. Chang, P.-W. Chou, C.-Y. Chen, H.-J. Liao, M.-B. Chen, Y.-H. Chu, W.-C. Wu, and H. Yamauchi, "A Large tolerant zigzag 8T SRAM with area-efficient decoupled differential sensing and fast write-back scheme," IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 815-827, Apr. 2011.
30. Z. Liu and V. Kursun, "Characterization of a novel nine-transistor SRAM Cell," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 4, pp. 488-492, Apr. 2008. (Pubitemid 351467531)
31. S. A. Verkila, S. K. Bondada, and B. S. Amrutur, "A 100 MHz to 1 GHz, 0.35V to 1.5Vsupply 256 64 SRAMblock using symmetrized 9T SRAM cell with controlled read," in Proc. Conf. VLSI Design, Jan. 2008, pp. 560-565.
32. M.-F. Chang, S.-W. Chang, P.-W. Chou, and W.-C. Wu, "A 130 mV SRAM with expanded write and read margins for subthreshold applications," IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 520-529, Feb. 2011.
33. B. H. Calhoun and A. P. Chandrakasan, "A 256 kb sub-threshold SRAM in 65 nm CMOS," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp. 2592-2601.
34. H. Noguchi et al., "A 10T non-precharge two-port SRAM for 74% power reduction in video processing," in IEEE Computer Society Annual Symp. VLSI Circuits (ISVLSI) Dig. Tech. Papers,March 2007, pp. 107-112. (Pubitemid 350147986)
35. T.-H. Kim, J. Liu, J. Keane, and C. H. Kim, "A high-density subthreshold SRAM with data-independent bitline leakage and virtual ground replica scheme," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 330-606.
36. J. P. Kulkarni, K. Kim, and K. Roy, "A 160 mV robust schmitt trigger based subthreshold SRAM," IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2303-2313, Oct. 2007. (Pubitemid 47483011)
37. J. Chen, L. T. Clark, and T.-H. Chen, "An ultra-low-power memory with a subthreshold power supply voltage," IEEE J. Solid-State Circuits, vol. 41, no. 10, pp. 2344-2353, Oct. 2006. (Pubitemid 44523672)
38. M. B. Chen, L. F. Chen, M.-F. Chang, S.-M. Yang, Y.-J. Kuo, J.-J. Wu, M.-S. Ho, H.-Y. Su, Y.-H. Chu, W.-C. Wu, T.-Y. Yang, and H. Yamauchi, "A 260 mV L-shaped 7T SRAM with Bit-Line (BL) swing expansion schemes based on boosted BL, asymmetric-V read-port, and offset cell VDD biasing techniques," in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2012, pp. 112-113.
39. S.-M. Yang and M.-F. Chang et al., "Low-voltage embedded NAND-ROM macros using data-aware sensing reference scheme for speed and power improvement," IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 611-623, Feb. 2013.
40. M.-F. Chang et al., "A high-speed 7.2-ns read-write random access 4-Mb embedded resistive RAM (ReRAM) macro using process-variation-tolerant current-mode read schemes," IEEE J. Solid-State Circuits, vol. 48, no. 3, pp. 878-891, March 2013.