A high-speed 7.2-ns read-write random access 4-Mb embedded resistive RAM (ReRAM) macro using process-variation-tolerant current-mode read schemes

IEEE Journal of Solid-State Circuits

Volumn 48, Issue 3, 2013, Pages 878-891

  Chang, Meng Fan ^a   Sheu, Shyh Shyuan ^b   Lin, Ku Feng ^a   Wu, Che Wei ^a   Kuo, Chia Chen ^a   Chiu, Pi Feng ^a,b   Yang, Yih Shan ^a   Chen, Yu Sheng ^a,b   Lee, Heng Yuan ^b   Lien, Chen Hsin ^a   Chen, Frederick T ^b   Su, Keng Li ^b   Ku, Tzu Kun ^b   Kao, Ming Jer ^b   Tsai, Ming Jinn ^b  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

Multilevel cell (MLC); read disturbance; resistive RAM (ReRAM); single level cell (SLC)

Indexed keywords

BIT LINES; CURRENT MODE; LOW-POWER OPERATION; MLC OPERATION; MULTI LEVEL CELL (MLC); NON-VOLATILE MEMORIES; PRE-CHARGE; RANDOM ACCESS; READ DISTURBANCE; READ OPERATION; READ SPEED; REFERENCE CURRENTS; RESISTANCE DISTRIBUTION; RESISTANCE VARIATIONS; RESISTIVE RAMS (RERAM); SINGLE-LEVEL CELL (SLC); SMALL FLUCTUATION; WRITE SPEED;

BIAS VOLTAGE;

RANDOM ACCESS STORAGE;

EID: 84874661685     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2012.2230515     Document Type: Article

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