A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric mosfet and forward body bias

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 356-357

  Nii, Koji ^a   Yabuuchi, Makoto ^a   Tsukamoto, Yasumasa ^a   Hirano, Yuuichi ^a   Iwamatsu, Toshiaki ^a   Kihara, Yuji ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN SOLUTIONS; DESIGN TECHNIQUE; FORWARD BODY BIAS; LOW STANDBY LEAKAGE; LOW VOLTAGE OPERATION; MOS-FET; RANDOM VARIATION; READ STABILITY; SENSOR NETWORK APPLICATIONS; SOLAR BATTERY; TECHNOLOGY SCALING; WRITE MARGIN;

DESIGN; ELECTRIC BATTERIES; MOSFET DEVICES; THERMOELECTRICITY;

STATIC RANDOM ACCESS STORAGE;

EID: 77952194725     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433817     Document Type: Conference Paper

References (7)

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2. Muhammad Khellah, Nam Sung Kim, Yibin Ye, Dinesh Somasekhar et al., "Process, Temperature, and Supply-Noise Tolerant 45 nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits," IEEE J. Solid-State Circuits, Vol. 44, No. 4, pp. 1199-1208, Apr., 2009.
3. Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto et al., "A 45nm Low-Standby- Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations," IEEE ISSCC Dig. Tech. Papers, pp. 326-327, Feb., 2007.
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5. Yen Huei Chen, Gary Chan et al., "A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD-min VLSIs, " IEEE J. Solid-State Circuits, Vol. 44, no. 4, pp. 1209-1215, Apr., 2009.
6. Jae-Joon Kim, Aditya Bansal, Rahul Rao et al., "Relaxing Conflict Between Read Stability and Writability in 6T SRAM Cell Using Asymmetric Transistors," IEEE Electron Device Letters, Vol. 30, No. 8, pp. 852-854, Aug., 2009.
7. Yuuichi Hirano et al., "A Novel Low-Power and High-Speed SOI SRAM With Actively Body-Bias Controlled (ABC) Technology for Emerging Generations," IEEE Transactions on Electron Devices, Vol. 55, No. 1, pp. 365-371, Jan., 2008.