A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-V TH read-port, and offset cell VDD biasing techniques

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2012, Pages 112-113

  Chen, Ming Pin ^a,b   Chen, Lai Fu ^a,b   Chang, Meng Fan ^a   Yang, Shu Meng ^a   Kuo, Yao Jen ^a   Wu, Jui Jen ^a   Ho, Mon Shu ^c   Su, Hsiu Yun ^b   Chu, Yuan Hua ^b   Wu, Wen Ching ^b   Yang, Tzu Yi ^b   Yamauchi, Hiroyuki ^d  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^c NATIONAL CHUNG HSING UNIVERSITY   (Taiwan)

^d FUKUOKA INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AREA EFFICIENT; BIASING TECHNIQUES; BIT LINES; CELL LAYOUT; L-SHAPED; OPERATION VOLTAGE; SRAM CELL; WRITE-BACK;

CELLS; CYTOLOGY; VLSI CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 84866615078     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2012.6243815     Document Type: Conference Paper

References (6)

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4. N. Verma, et al., ISSCC, pp. 328-329, Feb. 2007.
5. K. Miyaji, et al., IEEE JSSC, pp. 2180-2188, Sep. 2011.
6. K. Nii, et al. , ISSCC, pp. 356-357, Feb. 2010.