CMOS sensor arrays for high resolution die stress mapping in packaged integrated circuits

IEEE Sensors Journal

Volumn 13, Issue 6, 2013, Pages 2066-2076

  Chen, Yonggang ^a,b   Jaeger, Richard C ^a   Suhling, Jeffrey C ^a  

^a AUBURN UNIVERSITY   (United States)

^b Atlanta Design Center   (United States)

Author keywords

Complementary metal oxide semiconductor (CMOS); current mirror sensors; piezoresistance; PiFET; sensor array; sensors; stress

Indexed keywords

COMPLEMENTARY ARRAYS; COMPLEMENTARY-METAL-OXIDE SEMICONDUCTOR (CMOS); CURRENT MIRRORS; FINITE ELEMENT SIMULATIONS; HIGH SPATIAL DENSITY; NORMAL AND SHEAR STRESS; PIEZORESISTANCE; PIFET;

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FIELD EFFECT TRANSISTORS; MIRRORS; SENSOR ARRAYS; STRESS CONCENTRATION; STRESS MEASUREMENT; STRESSES;

SENSORS;

EID: 84876810287     PISSN: 1530437X     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSEN.2013.2247590     Document Type: Article

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