Three dimensional die surface stress measurements in delaminated and non-delaminated plastic packages

Proceedings - Electronic Components and Technology Conference

Volumn Part F133492, Issue , 1998, Pages 1223-1234

  Zou, Y ^a   Suhling, J C ^a   Jaeger, R C ^a   Ali, H ^b  

^a AUBURN UNIVERSITY   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; DIES; EXPANSION; FAILURE (MECHANICAL); NETWORK COMPONENTS; STRESS MEASUREMENT; SURFACE PROPERTIES; TESTING; THERMAL EXPANSION; ACOUSTIC MICROSCOPES; CRYSTAL ORIENTATION; DELAMINATION; ELECTRIC NETWORK ANALYSIS; ENCAPSULATION; MICROPROCESSOR CHIPS; SEMICONDUCTING SILICON; SENSORS; STRESS CONCENTRATION; STRESSES;

C-MODE SCANNING ACOUSTIC MICROSCOPIES; ENCAPSULATION PROCESS; MECHANICAL FAILURES; PIEZORESISTIVE STRESS SENSORS; ROOM TEMPERATURE RESISTANCE; TEMPERATURE COMPENSATED; THEORETICAL EQUATION; THREE DIMENSIONAL NONLINEAR FINITE ELEMENT;

STRESSES; ELECTRONICS PACKAGING;

COEFFICIENT OF THERMAL EXPANSION (CTE); PLASTIC ENCAPSULATED ELECTRONIC PACKAGES; QUAD FLAT PACKS (QFP);

EID: 0031645988     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.1998.678885     Document Type: Conference Paper

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