Die stress characterization using arrays of CMOS sensors

European Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 472-475

  Bradley, A T ^a   Jaeger, R C ^a   Suhling, J C ^a   Zou, Y ^a  

^a AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIE ENCAPSULATION; DIFFERENTIAL PAIRS; EXPERIMENTAL TEST; IN-PLANE NORMAL STRESS; MECHANICAL STRESS; MULTIPLEXING SCHEMES; TEMPERATURE COMPENSATED; TEMPERATURE-INSENSITIVE SENSORS;

CMOS INTEGRATED CIRCUITS; STRESS MEASUREMENT;

SENSORS;

EID: 79951678963     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIR.1998.186311     Document Type: Conference Paper

References (5)

1. D. A. Bittle, J. C. Suhling, et. al., "Piezoresistive stress sensors for structural analysis of electronic packages," Journal of Electronic Packaging, vol. 113, Sept. 1991, pp. 203-215.
2. R. C. Jaeger, J. C. Suhling, A. A. Anderson, "A (100) silicon stress test chip with optimized piezoresistive sensor rosettes," 44th Electronics Components and Technology Conference, May 1994, pp. 741-749.
3. R. C. Jaeger, R. Ramani, and J. Suhling, "Effects of stress-induced mismatches on CMOS analog circuits," Proceedings of the 1995 International VLSI TSA Symposium, Taipei, Taiwan, May 1995, pp. 354360.
4. R. C. Jaeger, R. Ramani, J. Suhling, and Y. Kang, "CMOS stress sensor circuits using piezoresistive field-effect transistors (PIFETs)," 1995 Symposium on VLSI Circuits Digest of Technical Papers, June 1995, pp. 43-44.
5. R. C. Jaeger, A. T. Bradley, J. C. Suhling, and Y. Zou, "FET mobility degradation and device mismatch due to packaging induced die stress," European Solid-State Circuits Conference, vol. 23, Sept. 1997, pp. 272275.