-
2
-
-
84875903904
-
Hybrid modeling and analysis of different throughsilicon-via(TSV)-based 3D power distribution networks
-
Dec
-
Z. Xu and J.-Q. Lu, "Hybrid modeling and analysis of different throughsilicon-via(TSV)-based 3D power distribution networks," in Proc. IEEE Int. Electrion Device Meeting, Dec. 2012, pp. 1-8.
-
(2012)
Proc. IEEE Int. Electrion Device Meeting
, pp. 1-8
-
-
Xu, Z.1
Lu, J.-Q.2
-
4
-
-
79960413400
-
Electromagnetic-SPICE modeling and analysis of 3D power network
-
Jun
-
Z. Xu, X. Gu, B. C. Webb, J. U. Knickerbocker, and J.-Q. Lu, "Electromagnetic-SPICE modeling and analysis of 3D power network," in Proc. IEEE Electron. Compon. Technol. Conf., Jun. 2011, pp. 2171-2178.
-
(2011)
Proc. IEEE Electron. Compon. Technol. Conf.
, pp. 2171-2178
-
-
Xu, Z.1
Gu, X.2
Webb, B.C.3
Knickerbocker, J.U.4
Lu, J.-Q.5
-
5
-
-
61549131161
-
3-D hyperintegration and packaging technologies for micronano systems
-
Jan
-
J.-Q. Lu, "3-D hyperintegration and packaging technologies for micronano systems," Proc. IEEE, vol. 97, no. 1, pp. 18-30, Jan. 2009.
-
(2009)
Proc. IEEE
, vol.97
, Issue.1
, pp. 18-30
-
-
Lu, J.-Q.1
-
6
-
-
0037233361
-
Beyond Moore's law: The interconnect era
-
Jan
-
J. Meindl, "Beyond Moore's law: The interconnect era," IEEE Comput. Sci. Eng., vol. 5, no. 1, pp. 20-24, Jan. 2003.
-
(2003)
IEEE Comput. Sci. Eng
, vol.5
, Issue.1
, pp. 20-24
-
-
Meindl, J.1
-
7
-
-
79960379635
-
Parasitics extraction, broadband modeling and sensitivity analysis of through-strata-via (TSV) in 3D integration/packaging
-
May
-
Z. Xu, X. Gu, and J.-Q. Lu, "Parasitics extraction, broadband modeling and sensitivity analysis of through-strata-via (TSV) in 3D integration/packaging," in Proc. IEEE/SEMI Adv. Semiconductor Manuf. Conf., May 2011, pp. 1-6.
-
(2011)
Proc. IEEE/SEMI Adv. Semiconductor Manuf. Conf.
, pp. 1-6
-
-
Xu, Z.1
Gu, X.2
Lu, J.-Q.3
-
8
-
-
61649110276
-
Threedimentional silicon integration
-
Nov
-
J. Knickerbocker, P. Andry, B. Dang, R. Horton, M. Interrante, C. Patel, R. Polastre, K. Sakuma, R. Sirdeshmukh, E. Sprogis, S. Sri-Jayantha, A. Stephens, A. Topol, C. Tsang, B. Webb, and S. Wright, "Threedimentional silicon integration," IBM J. Res. Devel., vol. 52, no. 6, pp. 537-664, Nov. 2008.
-
(2008)
IBM J. Res. Devel
, vol.52
, Issue.6
, pp. 537-664
-
-
Knickerbocker, J.1
Andry, P.2
Dang, B.3
Horton, R.4
Interrante, M.5
Patel, C.6
Polastre, R.7
Sakuma, K.8
Sirdeshmukh, R.9
Sprogis, E.10
Sri-Jayantha, S.11
Stephens, A.12
Topol, A.13
Tsang, C.14
Webb, B.15
Wright, S.16
-
10
-
-
80052028414
-
Through-strata-via (TSV) parasitics and broadband modeling for 3D integration/packaging
-
Sep.
-
Z. Xu and J.-Q. Lu, "Through-strata-via (TSV) parasitics and broadband modeling for 3D integration/packaging," IEEE Electron. Device Lett., vol. 32, no. 9, pp. 1278-1280, Sep. 2011.
-
(2011)
IEEE Electron. Device Lett
, vol.32
, Issue.9
, pp. 1278-1280
-
-
Xu, Z.1
Lu, J.-Q.2
-
11
-
-
61549106848
-
3-D technology assessment path-finding the technology design sweet spot
-
Jan
-
P. Marchal, B. Bougard, G. Katti, M. Stucchi, W. Dehaene, A. Papanikolaou, D. Verkest, B. Swinnen, and E. Beyne, "3-D technology assessment path-finding the technology design sweet spot," Proc. IEEE, vol. 97, no. 1, pp. 96-107, Jan. 2009.
-
(2009)
Proc. IEEE
, vol.97
, Issue.1
, pp. 96-107
-
-
Marchal, P.1
Bougard, B.2
Katti, G.3
Stucchi, M.4
Dehaene, W.5
Papanikolaou, A.6
Verkest, D.7
Swinnen, B.8
Beyne, E.9
-
12
-
-
80052032494
-
High-speed design and broadband modeling of through-strata-vias (TSVs) in 3D integration
-
Feb.
-
Z. Xu, and J.-Q. Lu, "High-speed design and broadband modeling of through-strata-vias (TSVs) in 3D integration," IEEE Trans. Compon., Packag. Manuf. Technol., vol. 1, no. 2, pp. 154-162, Feb. 2011.
-
(2011)
IEEE Trans. Compon., Packag. Manuf. Technol
, vol.1
, Issue.2
, pp. 154-162
-
-
Xu, Z.1
Lu, J.-Q.2
-
13
-
-
79960894955
-
Electrical performance and alignment investigation of wafer-level cu-oxide hybrid bonding schemes
-
Aug.
-
K.-N. Chen, Z. Xu, and J.-Q. Lu, "Electrical performance and alignment investigation of wafer-level cu-oxide hybrid bonding schemes," IEEE Electron Device Lett., vol. 32, no. 8, pp. 1119-1121, Aug. 2011.
-
(2011)
IEEE Electron Device Lett
, vol.32
, Issue.8
, pp. 1119-1121
-
-
Chen, K.-N.1
Xu, Z.2
Lu, J.-Q.3
-
14
-
-
0242443414
-
The evolution of monolithic and polylithic interconnect technology
-
Jun
-
J. Meindl, "The evolution of monolithic and polylithic interconnect technology," in Proc. IEEE Symp. VLSI Circuits Conf., Jun. 2002, pp. 2-5.
-
(2002)
Proc IEEE Symp. VLSI Circuits Conf.
, pp. 2-5
-
-
Meindl, J.1
-
15
-
-
78650950340
-
Characterization and modeling of solder balls and through-strata-vias (TSVs) in 3D architecture
-
Oct
-
Z. Xu, A. Beece, D. Zhang, Q. Chen, K. Rose, and J.-Q. Lu, "Characterization and modeling of solder balls and through-strata-vias (TSVs) in 3D architecture," in Proc. IEEE Conf. Electr. Perf. Electron. Packag. Syst., Oct. 2010, pp. 37-40.
-
(2010)
Proc. IEEE Conf. Electr. Perf. Electron. Packag. Syst.
, pp. 37-40
-
-
Xu, Z.1
Beece, A.2
Zhang, D.3
Chen, Q.4
Rose, K.5
Lu, J.-Q.6
-
16
-
-
84863251233
-
A novel chip-to-wafer (C2W) three-dimensional (3D) integration approach using a template for precise alignment
-
Apr
-
Q. Chen, D. Zhang, Z. Xu, A. Beece, R. Patti, Z. Tan, Z. Wang, L. Liu, and J.-Q. Lu, "A novel chip-to-wafer (C2W) three-dimensional (3D) integration approach using a template for precise alignment," J. Microelectron. Eng., vol. 92, pp. 15-18, Apr. 2012.
-
(2012)
J. Microelectron. Eng
, vol.92
, pp. 15-18
-
-
Chen, Q.1
Zhang, D.2
Xu, Z.3
Beece, A.4
Patti, R.5
Tan, Z.6
Wang, Z.7
Liu, L.8
Lu, J.-Q.9
-
18
-
-
61549115557
-
3-D data storage, power delivery, and RF/optical transceiver-case studies of 3-D integration from system design perspectives
-
Jan
-
T. Zhang, R. Micheloni, G. Zhang, Z. R. Huang, and J.-Q. Lu, "3-D data storage, power delivery, and RF/optical transceiver-case studies of 3-D integration from system design perspectives," Proc. IEEE, vol. 97, no. 1, pp. 161-174, Jan. 2009.
-
(2009)
Proc IEEE
, vol.97
, Issue.1
, pp. 161-174
-
-
Zhang, T.1
Micheloni, R.2
Zhang, G.3
Huang, Z.R.4
Lu, J.-Q.5
-
19
-
-
70549095281
-
Modeling and evaluation for electrical characteristics of through-strata-vias (TSVs) in three-dimensional integration
-
Sep
-
Z. Xu, A. Beece, T. Zhang, K. Rose, and J.-Q. Lu, "Modeling and evaluation for electrical characteristics of through-strata-vias (TSVs) in three-dimensional integration," in Proc. IEEE Int. Conf. 3D Syst. Integr., Sep. 2009, pp. 1-9.
-
(2009)
Proc. IEEE Int. Conf. 3D Syst. Integr.
, pp. 1-9
-
-
Xu, Z.1
Beece, A.2
Zhang, T.3
Rose, K.4
Lu, J.-Q.5
-
20
-
-
47949124019
-
Power delivery for 3D chip stacks: Physical modeling and design implication
-
Oct
-
G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. Meindl, "Power delivery for 3D chip stacks: Physical modeling and design implication," in Proc. IEEE Conf. Electr. Perf. Electron. Packag. Syst., Oct. 2007, pp. 205-208.
-
(2007)
Proc. IEEE Conf. Electr. Perf. Electron. Packag. Syst.
, pp. 205-208
-
-
Huang, G.1
Bakir, M.2
Naeemi, A.3
Chen, H.4
Meindl, J.5
-
21
-
-
67650321548
-
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
-
May
-
H. Yu, J. Ho, and L. He, "Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity," ACM Trans. Design Autom. Electron. Syst., vol. 14, no. 3, pp. 1-30, May 2009.
-
(2009)
ACM Trans. Design Autom. Electron. Syst
, vol.14
, Issue.3
, pp. 1-30
-
-
Yu, H.1
Ho, J.2
He, L.3
-
22
-
-
84863896354
-
Decoupling capacitor modeling and characterization for power supply noise in 3D systems
-
May
-
Z. Xu, C. Putnam, X. Gu, M. Scheuermann, K. Rose, B. Webb, J. U. Knickerbocker, and J.-Q. Lu, "Decoupling capacitor modeling and characterization for power supply noise in 3D systems," in Proc. 23rd IEEE/SEMI Adv. Semicond. Manuf. Conf., May 2012, pp. 414-419.
-
(2012)
Proc. 23rd IEEE/SEMI Adv. Semicond. Manuf. Conf.
, pp. 414-419
-
-
Xu, Z.1
Putnam, C.2
Gu, X.3
Scheuermann, M.4
Rose, K.5
Webb, B.6
Knickerbocker, J.U.7
Lu, J.-Q.8
-
23
-
-
79960988678
-
Design techniques to facilitate processor power delivery in 3D processor-DRAM integrated systems
-
Sep.
-
Q. Wu and T. Zhang, "Design techniques to facilitate processor power delivery in 3D processor-DRAM integrated systems," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 9, pp. 1655-1666, Sep. 2011.
-
(2011)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.19
, Issue.9
, pp. 1655-1666
-
-
Wu, Q.1
Zhang, T.2
-
24
-
-
33846213489
-
A 65-nm dual-core multithreaded Xeon processor with 16-MB L3 cache
-
Jan
-
R. Rusu, S. Tam, H. Muljono, D. Ayers, J. Chang, B. Cherkauer, J. Stinson, J. Benoit, R. Varada, J. Leung, R. Limaye, and S. Vora, "A 65-nm dual-core multithreaded Xeon processor with 16-MB L3 cache," IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 17-25, Jan. 2007.
-
(2007)
IEEE J. Solid-State Circuits
, vol.42
, Issue.1
, pp. 17-25
-
-
Rusu, R.1
Tam, S.2
Muljono, H.3
Ayers, D.4
Chang, J.5
Cherkauer, B.6
Stinson, J.7
Benoit, J.8
Varada, R.9
Leung, J.10
Limaye, R.11
Vora, S.12
-
25
-
-
16244362042
-
Feasibility of monolithic and 30-stacked DC-DC converters for microprocessors in 90nm technology generation
-
9.3, Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
-
G. Schrom, P. Hazucha, J. Hahn, V. Kursun, D. Gardner, S. Narendra, T. Karnik, and V. De, "Feasibility of monolithic and vertical-stacked 3D dc-dc converters for microprocessors in 90 nm technology generation," in Proc. IEEE Int. Symp. Low Power Electron. Design, Aug. 2004, pp. 263-268. (Pubitemid 40454723)
-
(2004)
Proceedings of the 2004 International Symposium on Lower Power Electronics and Design, ISLPED'04
, pp. 263-268
-
-
Schrom, G.1
Hazucha, P.2
Hahn, J.-H.3
Kursun, V.4
Gardner, D.5
Narendra, S.6
Karnik, T.7
De, V.8
-
27
-
-
84866856861
-
Modeling of power delivery into 3D chips on silicon interposer
-
May
-
Z. Xu, X. Gu, M. Scheuermann, K. Rose, B. Webb, J. Knickerbocker, and J.-Q. Lu, "Modeling of power delivery into 3D chips on silicon interposer," in Proc. IEEE Electron. Compon. Technol. Conf., May 2012, pp. 683-689.
-
(2012)
Proc. IEEE Electron. Compon. Technol. Conf.
, pp. 683-689
-
-
Xu, Z.1
Gu, X.2
Scheuermann, M.3
Rose, K.4
Webb, B.5
Knickerbocker, J.6
Lu, J.-Q.7
-
28
-
-
79953084400
-
Power delivery design for 3-D ICs using different through-silicon-via (TSV) technologies
-
Apr.
-
N. Khan, S. Alam, and S. Hassoun, "Power delivery design for 3-D ICs using different through-silicon-via (TSV) technologies," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 4, pp. 647-658, Apr. 2010.
-
(2010)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.19
, Issue.4
, pp. 647-658
-
-
Khan, N.1
Alam, S.2
Hassoun, S.3
-
29
-
-
84875907368
-
A multistory power delivery techniques for 3D integrated circuits
-
Aug
-
P. Jain, T. Kim, J. Keane, and C. Kim, "A multistory power delivery techniques for 3D integrated circuits," in Proc. IEEE Int. Symp. Low Power Electron. Design, Aug. 2009, pp. 1-6.
-
(2009)
Proc. IEEE Int. Symp. Low Power Electron. Design
, pp. 1-6
-
-
Jain, P.1
Kim, T.2
Keane, J.3
Kim, C.4
-
30
-
-
77950977359
-
3D stacked power distribution considering substrate coupling
-
Oct
-
A. Shayan, X. Hu, W. Zhang, C. Cheng, A. Engin, X. Chen, and M. Popovich, "3D stacked power distribution considering substrate coupling," in Proc. IEEE Int. Conf. Comput. Design, Oct. 2009, pp. 225-230.
-
(2009)
Proc. IEEE Int. Conf. Comput. Design
, pp. 225-230
-
-
Shayan, A.1
Hu, X.2
Zhang, W.3
Cheng, C.4
Engin, A.5
Chen, X.6
Popovich, M.7
-
31
-
-
84866911870
-
Three-dimensional coaxial through-siliconvia (TSV) design
-
Oct.
-
Z. Xu and J.-Q. Lu, "Three-dimensional coaxial through-siliconvia (TSV) design," IEEE Electron Device Lett., vol. 33, no. 10, pp. 1441-1443, Oct. 2012.
-
(2012)
IEEE Electron Device Lett
, vol.33
, Issue.10
, pp. 1441-1443
-
-
Xu, Z.1
Lu, J.-Q.2
-
32
-
-
34548348855
-
Understanding voltage variations in chip multiprocessors using a distributed powerdelivery network
-
Apr
-
M. Gupta, J. Oatley, R. Joseph, G. Wei, and D. Brooks, "Understanding voltage variations in chip multiprocessors using a distributed powerdelivery network," in Proc. Design, Autom. Test Conf., Apr. 2007, pp. 1-6.
-
(2007)
Proc. Design, Autom. Test Conf
, pp. 1-6
-
-
Gupta, M.1
Oatley, J.2
Joseph, R.3
Wei, G.4
Brooks, D.5
-
33
-
-
10444284956
-
Power delivery system performance optimization of a printed circuit board with multiple microprocessors
-
Jun
-
O. Mandhana and J. Zhao, "Power delivery system performance optimization of a printed circuit board with multiple microprocessors," in Proc. IEEE Electron. Compon. Technol. Conf., Jun. 2004, pp. 581-588.
-
(2004)
Proc. IEEE Electron. Compon. Technol. Conf.
, pp. 581-588
-
-
Mandhana, O.1
Zhao, J.2
-
34
-
-
29244447761
-
3D module placement for congestion and power noise reduction
-
S11.3S, GLSVSI'05 - Proceedings of the 2005 ACM Great
-
J. Minz, S. Lim, and C. Koh, "3D module placement for congestion and power noise reduction," in Proc. ACM Great Lakes Symp. VLSI Conf., Apr. 2005, pp. 458-461. (Pubitemid 41828881)
-
(2005)
Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
, pp. 458-461
-
-
Minz, J.R.1
Lim, S.K.2
Koh, C.-K.3
-
35
-
-
78751554802
-
Processing material evaluation and ultra-wideband modeling of through-strata-bia (TSV) in 3D integrated circuits and systems
-
Nov
-
Z. Xu, A. Beece, D. Zhang, Q. Chen, K. Rose, and J.-Q. Lu, "Processing material evaluation and ultra-wideband modeling of through-strata-bia (TSV) in 3D integrated circuits and systems," in Proc. IEEE Int. Conf. Solid-State Integr. Circuit Technol., Nov. 2010, pp. 1-6.
-
(2010)
Proc. IEEE Int. Conf. Solid-State Integr. Circuit Technol.
, pp. 1-6
-
-
Xu, Z.1
Beece, A.2
Zhang, D.3
Chen, Q.4
Rose, K.5
Lu, J.-Q.6
-
36
-
-
79955970977
-
Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network
-
Nov
-
Z. Xu, A. Beece, D. Zhang, Q. Chen, K.-N. Chen, K. Rose, and J.-Q. Lu, "Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network," in Proc. IEEE Int. Conf. 3D Syst. Integr., Nov. 2010, pp. 1-8.
-
(2010)
Proc. IEEE Int. Conf. 3D Syst. Integr.
, pp. 1-8
-
-
Xu, Z.1
Beece, A.2
Zhang, D.3
Chen, Q.4
Chen, K.-N.5
Rose, K.6
Lu, J.-Q.7
-
37
-
-
10444284956
-
Power delivery system performance optimization of a printed circuit board with multiple microprocessors
-
Jun
-
O. P. Mandhana and J. Zhao, "Power delivery system performance optimization of a printed circuit board with multiple microprocessors," in Proc. IEEE Electron. Compon. Technol. Conf., Jun. 2004, pp. 581-588.
-
(2004)
Proc. IEEE Electron. Compon. Technol. Conf.
, pp. 581-588
-
-
Mandhana, O.P.1
Zhao, J.2
-
38
-
-
84866842349
-
Multiple voltage-supplies in TSV-based three-dimensional (3D) power distribution networks
-
May
-
Z. Xu, X. Gu, M. Scheuermann, K. Rose, B. Webb, J. Knickerbocker, and J.-Q. Lu, "Multiple voltage-supplies in TSV-based three-dimensional (3D) power distribution networks," in Proc. IEEE Electron. Compon. Technol. Conf., May 2012, pp. 1819-1825.
-
(2012)
Proc. IEEE Electron. Compon. Technol. Conf.
, pp. 1819-1825
-
-
Xu, Z.1
Gu, X.2
Scheuermann, M.3
Rose, K.4
Webb, B.5
Knickerbocker, J.6
Lu, J.-Q.7
-
39
-
-
84875899349
-
-
Canonsburg, PA [Online]
-
Manual of ANSYS Q3D v.11., Canonsburg, PA, (2012) [Online]. Available: http://www.ansys.com/Products/Simulation+Technology/Electromagnetics/ High-Performance+Electronic+Design/ANSYS+Q3D+ Extractor
-
(2012)
Manual of ANSYS Q3D
, vol.11
-
-
-
40
-
-
84897581342
-
-
[Online]
-
Intel Xeon Processor. (2012) [Online]. Available: http://www.intel. com/content/www/us/en/processors/xeon/xeon-processor-e7-family.html
-
(2012)
Intel Xeon Processor
-
-
-
41
-
-
0033670992
-
Model and analysis for combined package and on-chip power grid simulation
-
Jul
-
R. Panda, D. Blaauw, R. Chaudhry, V. Zolotov, B. Young, and R. Ramaraju, "Model and analysis for combined package and on-chip power grid simulation," in Proc. IEEE Int. Symp. Low Power Electron. Design, Jul. 2000, pp. 179-184.
-
(2000)
Proc. IEEE Int. Symp. Low Power Electron. Design
, pp. 179-184
-
-
Panda, R.1
Blaauw, D.2
Chaudhry, R.3
Zolotov, V.4
Young, B.5
Ramaraju, R.6
|