Demonstration and electrical performance investigation of wafer-level cu oxide hybrid bonding schemes

IEEE Electron Device Letters

Volumn 32, Issue 8, 2011, Pages 1119-1121

  Chen, Kuan Neng ^a   Xu, Zheng ^b   Lu, Jian Qiang ^b  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

3 D integration; Hybrid wafer bonding; wafer level

Indexed keywords

3-D INTEGRATION; ALIGNMENT ACCURACY; CU OXIDE; ELECTRICAL PERFORMANCE; ELECTRICAL SIMULATION; HYBRID BONDING; HYBRID WAFER BONDING; MECHANICAL BONDS; PASSIVE ELEMENTS; RELIABILITY PERFORMANCE; SIMULTANEOUS FORMATION; UNDERFILLS; WAFER LEVEL;

ALIGNMENT; FREQUENCY RESPONSE; INTEGRATION; THREE DIMENSIONAL;

WAFER BONDING;

EID: 79960894955     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2157657     Document Type: Article

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