Power delivery system performance optimization of a printed circuit board with multiple microprocessors

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2004, Pages 581-588

  Mandhana, Om P ^a   Zhao, Jin ^b  

^a MOTOROLA INC   (United States)

^b Sigrity Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MULTIPLE MICROPROCESSORS; PACKAGE TERMINALS; POWER DELIVERY SYSTEMS; SIGNAL TRANSMISSION;

DATA REDUCTION; ELECTRIC IMPEDANCE; ELECTRIC POTENTIAL; FREQUENCIES; PRINTED CIRCUIT BOARDS; RESONANCE;

MICROPROCESSOR CHIPS;

EID: 10444284956     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. PowerSI by SIGRITY, Inc.
3. W. Beyne, C. Yuan, J. Kim, and M. Swaminathan, "Modeling and analysis of Power Distribution Network for Gigabit Applications", Proceedings of the International Symposium on Quality Electronic Design (ISQED'03)
4. th International Conference on VLSI, Jan. 2000
5. L. Smith, et al., "Power distribution system design methodology and capacitor selection for modern CMOS technology", IEEE Trans. Advanced Packag., pp. 284-290, vol. 22, August 1999.
6. SPEED2000 by SIGRITY, Inc.