Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network

IEEE 3D System Integration Conference 2010, 3DIC 2010

Volumn , Issue , 2010, Pages

  Xu, Zheng ^a   Beece, Adam ^a   Zhang, Dingyou ^a   Chen, Qianwen ^a   Chen, Kuan Neng ^b   Rose, Kenneth ^a   Lu, Jian Qiang ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

3D integration; Crosstalk; Modeling; TSV

Indexed keywords

3-D INTEGRATION; COUPLING NOISE; CRITICAL COMPONENT; CROSSTALK NOISE; ELECTROMAGNETIC FIELD SOLVER; FAR END CROSSTALK; FREQUENCY DEPENDENT; FREQUENCY DOMAINS; HIGH-SPEED OPERATION; MODELING; MOORE'S LAW; NEAR END CROSS TALKS; RISETIMES; SPICE SIMULATORS; SUBSTRATE RESISTIVITY; SWITCHING PATTERNS; TIME DOMAIN; TSV;

CROSSTALK; ELECTROMAGNETIC FIELDS; INTEGRATION; SPICE;

THREE DIMENSIONAL;

EID: 79955970977     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/3DIC.2010.5751477     Document Type: Conference Paper

References (13)

1. J.-Q. Lu,"3-D Hyperintegration and Packaging Technologies for Micro- Nano Systems," Proceeding of IEEE, Vol. 97, no. 1, pp. 18-30, Jan. 2009.
2. R.J. Gutmann, J.-Q. Lu, R.P. Kraft, P.M. Belemjian, O. Erdogan, J. Barrett, and J.F. McDonald, "IP Core-based Design, High-speed Processor Design and Multiplexing LAN architectures enabled by 3D Wafer Bonding Technologies," in DesignCon 2001: Wireless and Optical Broadband Design Conference, 2001, paper no.: WB-13.
3. Q. Wu, K. Rose, J.-Q. Lu, and T. Zhang, "Impacts of Though-DRAM Power Vias in 3D Processor-DRAM Integrated Systems," IEEE International 3D System Integration Conference, San Francisco, CA, Sept. 2009.
4. K.C. Saraswat and F. Mohammadi, "Effect of Interconnection Scaling on Time Delay of VLSI circuits," IEEE Trans. Electron Devices, Vol. 29, pp. 645-50, 1982.
5. J.-Q. Lu, J.J. McMahon1, and R.J. Gutmann, "3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer-Level Bonding Interfaces", in Materials and Technologies for 3-D Integration, MRS. Vol. 1112, Boston, MA, Dec. 2008.
6. R.J. Gutmann, J.-Q. Lu, S. Pozder, Y. Kwon, D. Menke, A. Jindal, M. Celik, M. Rasco, J.J. McMahon, K. Yu and T.S. Cale, "A wafer-level 3D IC technology platform," Proc. Advanced Metallization Conference, 2003, pp. 19-26.
7. N. Khan, V.S. Rao, S. Lim, H.S. We, V. Lee, Z.X. Wu, L. Yang, and E. Liao, "Development of 3D Silicon Module with TSV for System in Packaging," Electronic Components and Technology Conference, Lake Buena Vista, FL, May 2008, pp. 550-555.
8. B. Wunderle, R. Mrossko. O. Wittler, F. Kaulfersch, P. Ramm, B. Michel, and H. Reichl, "Thermo-mechanical Reliability of 3D-integrated Microstructures in Stacked Silicon," Material Research Society Proc. Vol. 970, pp. 67-78, 2006.
9. Z. Xu, A. Beece, T. Zhang, K. Rose, J.-Q. Lu, "Modeling and Evaluation for Electrical Characteristics of Through-Strata-Vias (TSVs) in Three- Dimensional Integration," IEEE International 3D System Integration Conference (3D IC), San Francisco, CA, Sept. 2009.
10. Z. Xu, A. Beece, D.Y. Zhang, Q.W. Chen, K. Rose, J.-Q. Lu, "High- Speed Design and Broadband Modeling of Through-Strata-Vias (TSVs) in 3D Integration," IEEE Trans. on Advanced Packaging, in press.
11. B. Young, "Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages", Prentice Hall PTR, 2001.
12. T. Lee, "The Design of CMOS Radio-Frequency Integrated Circuits, Cambridge University Press, second edition 2004.
13. J. Rogers and C. Plett, "Radio Frequency Integrated Circuit Design", Artech House, 2003.