Parasitics extraction, wideband modeling and sensitivity analysis of through-strata-via (TSV) in 3D integration/packaging

ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings

Volumn , Issue , 2011, Pages

  Xu, Zheng ^a   Gu, Xiaoxiong ^b   Lu, Jian Qiang ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

3D integration; modeling; packaging; RLGC extraction; sensitivity analysis; TSV

Indexed keywords

3-D INTEGRATION; 3D SYSTEMS; ELECTRICAL CHARACTERISTIC; ELECTROMAGNETIC SIMULATORS; EMPIRICAL CALCULATIONS; EXTRACTION TECHNIQUES; FREQUENCY RANGES; FULL-WAVE SIMULATIONS; LAYER THICKNESS; PARASITICS; PHYSICAL DESIGN; QUASI-STATIC; RETURN LOSS; RLGC EXTRACTION; SIGNAL GAIN; SPICE MODEL; SPICE SIMULATORS; TSV; WIDE-BAND; WIDEBAND MODELING;

CHIP SCALE PACKAGES; MANUFACTURE; SEMICONDUCTOR DEVICE MANUFACTURE; SENSITIVITY ANALYSIS; SIMULATORS; SPICE;

THREE DIMENSIONAL;

EID: 79960379635     PISSN: 10788743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASMC.2011.5898175     Document Type: Conference Paper

References (9)

1. J.-Q. Lu, "3-D hyperintegration and packaging technologies for micronano systems", in Proc. IEEE, vol. 97, no. 1, Jan. 2009, pp. 18-30.
2. Manual of Ansoft HFSS v12 2010.
3. Manual of Ansoft Q3D v9 2010.
4. Manual of Agilent ADS 2009.
5. H. A. Wheeler, "Formulas for the skin effect", Proc. the Institute of Radio Engineers, vol. 30, pp. 412-424, Sept. 1942.
6. T. Liang, S. Hall, H. Heck, and G. Brist, "A practical method for modeling PCB transmission lines with conductor surface roughness and wideband dielectric properties, ", IEEE MTT-S International Microwave Symposium Digest, San Francisco, 2006, pp1780-1783. (Pubitemid 46924614)
7. J. S. Pak, J. Cho, J. Kim, J. Lee, H. Lee, K. Park, and J. Kim, "Slow wave and dielectric quasi-TEM modes of metal-insulator-semiconductor (MIS) structure through silicon via (TSV) in signal propagation and power delivery in 3D chip package", Electronic Components and Technology Conference, Las Vegas, NV, June 2010, pp 667-672.
8. Z. Xu, A. Beece, T. Zhang, K. Rose, and J.-Q. Lu, "Modeling and evaluation for electrical characteristics of through-strata-vias (TSVs) in three-dimensional integration", IEEE International 3D System Integration Conference, San Francisco, CA, Sept. 2009.
9. G. Katti, M. Stucchi, K. D. Meyer and W. Dehaene, "Electrical modeling and characterization of through silicon via for three-dimensional ICs", IEEE Tran. on Electron Devices, vol. 57, no. 1, Jan. 2010, pp. 256-261.