Through-strata-via (TSV) parasitics and wideband modeling for three-dimensional integration/packaging

IEEE Electron Device Letters

Volumn 32, Issue 9, 2011, Pages 1278-1280

  Xu, Zheng ^a   Lu, Jian Qiang ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

3 D integration; Modeling; packaging; RLGC extraction; sensitivity analysis; through strata via (TSV)

Indexed keywords

3-D INTEGRATION; ANALYTICAL CALCULATION; ELECTRICAL CHARACTERISTIC; FREQUENCY RANGES; LAYER THICKNESS; PARASITICS; PHYSICAL DESIGN; RETURN LOSS; RLGC EXTRACTION; SIGNAL GAIN; SPICE MODEL; THREE DIMENSIONAL INTEGRATION; THROUGH-STRATA-VIA (TSV); WIDE-BAND; WIDEBAND MODELING;

SENSITIVITY ANALYSIS;

THREE DIMENSIONAL;

EID: 80052028414     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2011.2158511     Document Type: Article

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