High-speed design and broadband modeling of through-strata-vias (TSVs) in 3D integration

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 1, Issue 2, 2011, Pages 154-164

  Xu, Zheng ^a   Lu, Jian Qiang ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

Broadband model; equivalent circuit; three dimensional (3D) integration; through strata via (TSV)

Indexed keywords

BROADBAND MODEL; BROADBAND MODELING; ELECTRICAL PERFORMANCE; ELECTROMAGNETIC FIELD SOLVER; ELECTRONIC DESIGN AUTOMATION TOOLS; EQUIVALENT CIRCUIT MODEL; THREE DIMENSIONAL (3D) INTEGRATION; THROUGH-STRATA-VIA (TSV);

CIRCUIT THEORY; ELECTROMAGNETIC FIELDS; EQUIVALENT CIRCUITS; INTEGRATION; THREE DIMENSIONAL COMPUTER GRAPHICS;

THREE DIMENSIONAL;

EID: 80052032494     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2010.2101693     Document Type: Article

References (11)

1. J.-Q. Lu, "3-D hyperintegration and packaging technologies for micronano systems," Proc. IEEE, vol. 97, no. 1, pp. 18-30, Jan. 2009.
2. J. D. Meindl, "The evolution of monolithic and polylithic interconnect technology," in IEEE Symp. VLSI Circuits, Honolulu, HI, Jun. 2002, pp. 2-5.
3. Q. Wu, K. Rose, J.-Q. Lu, and T. Zhang, "Impacts of though-DRAM power vias in 3D processor-DRAM integrated systems," in IEEE Int. 3D Syst. Integration Conf., San Francisco, CA, Sep. 2009, pp. 1-6.
4. J.-Q. Lu, J. J. McMahon, and R. J. Gutmann, "3D integration using adhesive, metal, and metal/adhesive as wafer-level bonding interfaces," in Materials Technol. 3-D Integrat., Boston, MA, Dec. 2008, vol. 1112, pp. 69-80.
5. N. Khan, V. S. Rao, S. Lim, H. S. We, V. Lee, Z. X. Wu, L. Yang, and E. Liao, "Development of 3D silicon module with TSV for system in packaging," in Electron. Compon. Technol. Conf., Lake Buena Vista, FL, May 2008, pp. 550-555.
6. B. Wunderle, R. Mrossko, O. Wittler, F. Kaulfersch, P. Ramm, B. Michel, and H. Reichl, "Thermo-mechanical reliability of 3D-integrated microstructures in stacked silicon," in Material Res. Soc. Proc., 2006, vol. 970, pp. 67-78.
7. Manual of Ansoft HFSS v11 2009.
8. Z. Xu, A. Beece, T. Zhang, K. Rose, and J.-Q. Lu, "Modeling and evaluation for electrical characteristics of through-strata-vias (TSVs) in three-dimensional integration," in IEEE Int. 3D System Integration Conf., San Francisco, CA, Sep. 2009.
9. C. Ryu, D. Chung, J. Lee, K. Y. Lee, T. S. Oh, and J. Kim, "High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package," in IEEE 14th Topical Meeting Electrical Performance Electron Packag., Austin, TX, Oct. 2005, pp. 151-154.
10. D. M. Jang, C. Ryu, K. Y. Lee, B. H. Cho, J. Kim, T. S. Oh, W. J. Lee, and J. Yu, "Development and evaluation of 3-D SiP with vertically interconnected through silicon vias (TSV)," in Electron. Compon. Technol. Conf., Reno, NV, May 2007, pp. 847-852.
11. Manual of Advanced Design System Agilent Technologies, 2009.