-
1
-
-
47949124019
-
Power delivery for 3d chip stacks: Physical modeling and design implication
-
Oct. 2007
-
G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. D. Meindl, "Power delivery for 3d chip stacks: Physical modeling and design implication," in IEEE Electrical Performance of Electronic Packaging, 2007, Oct. 2007, pp. 205-208.
-
(2007)
IEEE Electrical Performance of Electronic Packaging
, pp. 205-208
-
-
Huang, G.1
Bakir, M.2
Naeemi, A.3
Chen, H.4
Meindl, J.D.5
-
2
-
-
58049122127
-
3d power distribution network co-design for nanoscale stacked silicon ics
-
A. Shayan, X. Hu, H. Peng, M. Popovich, W. Zhang, C. Cheng, L. Chua-Eoan, and X. Chen, 3d power distribution network co-design for nanoscale stacked silicon ics," Electrical Performance of Electronic Packaging, 2008.
-
(2008)
Electrical Performance of Electronic Packaging
-
-
Shayan, A.1
Hu, X.2
Peng, H.3
Popovich, M.4
Zhang, W.5
Cheng, C.6
Chua-Eoan, L.7
Chen, X.8
-
3
-
-
28344435928
-
Physical design for 3d system on package
-
S. Lim, "Physical design for 3d system on package," IEEE Trans. Design and Test of Computers, vol.22, no.6, 2005.
-
(2005)
IEEE Trans. Design and Test of Computers
, vol.22
, Issue.6
-
-
Lim, S.1
-
4
-
-
85088005500
-
Reliability aware through silicon via planning for nanoscale stacked silicon ics
-
A. Shayan, X. Hu, H. Peng, C. Cheng, W. Yu, M. Popovich, X. Chen, and T. Toms, "Reliability aware through silicon via planning for nanoscale stacked silicon ics," Design Automation and Test in Europe, 2009.
-
(2009)
Design Automation and Test in Europe
-
-
Shayan, A.1
Hu, X.2
Peng, H.3
Cheng, C.4
Yu, W.5
Popovich, M.6
Chen, X.7
Toms, T.8
-
5
-
-
50949114112
-
Resistance to electromigration of purely intermetallic micro-bump interconnections for 3d-device stacking
-
R. Labie, W. Ruythooren, K. Baert, E. beyne, and B. Swinnen, "Resistance to electromigration of purely intermetallic micro-bump interconnections for 3d-device stacking," Interconnect Technology Conference, 2008.
-
(2008)
Interconnect Technology Conference
-
-
Labie, R.1
Ruythooren, W.2
Baert, K.3
Beyne, E.4
Swinnen, B.5
-
6
-
-
51349168308
-
Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps
-
May 2008
-
C. Selvanayagam, J. H. Lau, X. Zhang, S. K. W. Seah, V. Kripesh, and T. C. Chai, "Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps," in Electronics Components and Technology Conference, 2008, May 2008, pp. 1073-1081.
-
(2008)
Electronics Components and Technology Conference
, pp. 1073-1081
-
-
Selvanayagam, C.1
Lau, J.H.2
Zhang, X.3
Seah, S.K.W.4
Kripesh, V.5
Chai, T.C.6
-
7
-
-
34748909644
-
3D power delivery for microprocessors and high-performance asics
-
2007Mar
-
J. Sun, J.-Q. Lu, D. Giuliano, T. P. Chow, and R. J. Gutmann, "3D Power Delivery for Microprocessors and High-Performance ASICs," in IEEE 22nd Applied Power Electronics Conference, 2007, Mar. 2007, pp. 127-133.
-
(2007)
IEEE 22nd Applied Power Electronics Conference
, pp. 127-133
-
-
Sun, J.1
Lu, J.-Q.2
Giuliano, D.3
Chow, T.P.4
Gutmann, R.J.5
-
8
-
-
0036684625
-
Substrate noise generation in complex digital, systems: Efficient modeling and simulation methodology and experimental verification
-
M. Heijningen, M. Badaroglu, S. Donnay, G. Gielen, and H. D. Man, "Substrate noise generation in complex digital, systems: efficient modeling and simulation methodology and experimental verification," IEEE Journal of Solid-State Circuits, 2002.
-
(2002)
IEEE Journal of Solid-State Circuits
-
-
Heijningen, M.1
Badaroglu, M.2
Donnay, S.3
Gielen, G.4
Man, H.D.5
-
9
-
-
39049141159
-
Die stacking technology for terabit chip-to-chip communications
-
A. Rahman, J. Trezza, B. New, and S. Trimberger, "Die stacking technology for terabit chip-to-chip communications," Custom Integrated Circuits Conference, 2006.
-
(2006)
Custom Integrated Circuits Conference
-
-
Rahman, A.1
Trezza, J.2
New, B.3
Trimberger, S.4
-
11
-
-
77950995325
-
-
"http://www.ansoft.com/hfss/."
-
-
-
-
12
-
-
51349094381
-
High rf performance tsv silicon, carrier for high frequency application
-
S. Ho, S. Yoon, Q. Zhou, K. Pasad, V. Kripesh, and J. Lau, "High rf performance tsv silicon, carrier for high frequency application," Electronic Components and Technology Conference, 2008.
-
(2008)
Electronic Components and Technology Conference
-
-
Ho, S.1
Yoon, S.2
Zhou, Q.3
Pasad, K.4
Kripesh, V.5
Lau, J.6
-
13
-
-
33747170137
-
Loss characteristics of silicon substrate with different resistivities
-
R. Yang, C. Hung, Y. Su, M. Weng, and H. Wu, "Loss characteristics of silicon substrate with different resistivities," Microwave and Optical Tech. Lett., 2006.
-
(2006)
Microwave and Optical Tech. Lett.
-
-
Yang, R.1
Hung, C.2
Su, Y.3
Weng, M.4
Wu, H.5
-
14
-
-
0026908091
-
S-parameter-based interconnect transmission line characterization
-
W. Eisenstadt and Y. Eo, "S-parameter-based interconnect transmission line characterization," IEEE trans. on Components, Hybrids, and Manufacturing Technology, vol.15, no.4, 1992.
-
(1992)
IEEE Trans. on Components, Hybrids, and Manufacturing Technology
, vol.15
, Issue.4
-
-
Eisenstadt, W.1
Eo, Y.2
-
15
-
-
77951003907
-
-
"http://www.ansoft.com/products/si/q3d-extractor."
-
-
-
-
16
-
-
52949101707
-
Fast power network analysis with multiple clock domains
-
Oct.
-
W. Zhang, L. Zhang, R. Shi, H. Peng, Z. Zhu, L. Chua-Eoan, R. Murgai, T. Shibuya, N. Ito, and C. K. Cheng, "Fast Power Network Analysis with Multiple Clock Domains," in 25th International Conference on Computer Design, 2007, Oct. 2007, pp. 456-463.
-
(2007)
25th International Conference on Computer Design
, vol.2007
, pp. 456-463
-
-
Zhang, W.1
Zhang, L.2
Shi, R.3
Peng, H.4
Zhu, Z.5
Chua-Eoan, L.6
Murgai, R.7
Shibuya, T.8
Ito, N.9
Cheng, C.K.10
-
18
-
-
34247581920
-
Ower and reliability management of socs
-
T. Rosing, K. Mihic, and G. D. Micheli, "ower and reliability management of socs," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2007.
-
(2007)
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
-
-
Rosing, T.1
Mihic, K.2
Micheli, G.D.3
-
19
-
-
35348890136
-
Thermomechanical analysis of thru-silicon-via based high density compliant interconnect
-
P. Arunasalam, F. Zhou, H. Ackler, and B. Sammakia, " Thermomechanical analysis of thru-silicon-via based high density compliant interconnect," Electronic Components and Technology Conference, 2007.
-
(2007)
Electronic Components and Technology Conference
-
-
Arunasalam, P.1
Zhou, F.2
Ackler, H.3
Sammakia, B.4
|