Design techniques to facilitate processor power delivery in 3-D processor-DRAM integrated systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 9, 2011, Pages 1655-1666

  Wu, Qi ^a   Zhang, Tong ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

3 D integration; decoupling capacitor; instructions per cycle (IPC); IR drop; power delivery; processor DRAM integrated system; through silicon via (TSV)

Indexed keywords

3-D INTEGRATION; DECOUPLING CAPACITOR; INSTRUCTIONS PER CYCLES; INTEGRATED SYSTEMS; IR DROP; POWER DELIVERY; THROUGH-SILICON VIA (TSV);

CAPACITORS; DESIGN; DIES; ELECTRIC CONVERTERS; ELECTRIC POWER TRANSMISSION; ELECTRONICS PACKAGING; INTEGRATED CONTROL; SPICE; THREE DIMENSIONAL;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 79960988678     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2053565     Document Type: Article

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