Design and architectural assessment of 3-D resistive memory technologies in FPGAs

IEEE Transactions on Nanotechnology

Volumn 12, Issue 1, 2013, Pages 40-50

  Gaillardon, Pierre Emmanuel ^a   Sacchetto, Davide ^a   Beneventi, Giovanni Betti ^b,c   Ben Jamaa, M Haykel ^b   Perniola, Luca ^b   Clermidy, Fabien ^b   O'Connor, Ian ^d,e   De Micheli, Giovanni ^a  

^a EPFL   (Switzerland)

^b DIF   (France)

^c UNIVERSITY OF BOLOGNA   (Italy)

^d ECOLE CENTRALE DE LYON   (France)

^e ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

3 D integration; nonvolatile memory; oxide memory; phase change memory; programmable logic arrays; RRAM

Indexed keywords

3-D INTEGRATION; NON-VOLATILE MEMORIES; PHASE CHANGES; PROGRAMMABLE LOGIC ARRAY; RRAM;

PHASE CHANGE MEMORY; PLATINUM; TABLE LOOKUP;

RANDOM ACCESS STORAGE;

EID: 84872167658     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2012.2226747     Document Type: Article

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