FPGA based on integration of CMOS and RRAM

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 11, 2011, Pages 2023-2032

  Tanachutiwat, Sansiri ^a   Liu, Ming ^b   Wang, Wei ^a  

^a STATE UNIVERSITY OF NEW YORK   (United States)

^b INSTITUTE OF MICROELECTRONICS   (China)

Author keywords

3 D integration; CMOS nano hybrid circuit; field programmable gate array (FPGA); nanojunction; resistive RAM (RRAM)

Indexed keywords

3-D INTEGRATION; BLOCK MEMORIES; CMOS COMPATIBLE; DENSITY ENHANCEMENT; GATE ARRAYS; HYBRID CIRCUIT; LOWER-POWER CONSUMPTION; NANOJUNCTIONS; POWER REDUCTIONS; RE-CONFIGURABLE; RESISTIVE RAM (RRAM); ROUTING SWITCHES; SIMULATION RESULT;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MEMORY ARCHITECTURE; RECONFIGURABLE HARDWARE; THREE DIMENSIONAL;

RANDOM ACCESS STORAGE;

EID: 80052913208     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2063444     Document Type: Article

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