Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 406-407

  Liauw, Young Yang ^a   Zhang, Zhiping ^a   Kim, Wanki ^a   Gamal, Abbas El ^a   Wong, S Simon ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

65NM CMOS TECHNOLOGY; CMOS PROCESSS; CONFIGURATION MEMORY; DIE AREA; MEMORY TECHNOLOGY; NON-VOLATILE; PERFORMANCE GAIN; PROGRAMMABLE LOGIC DEVICE; RESISTIVE RAMS (RRAM); STACKED CONFIGURATION;

CMOS INTEGRATED CIRCUITS; LOGIC DEVICES; THREE DIMENSIONAL;

STATIC RANDOM ACCESS STORAGE;

EID: 84860673822     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6177067     Document Type: Conference Paper

References (6)

1. M. Lin, et al., "Performance benefits of monolithically stacked 3D-FPGA," Int. Symposium on Field-Programmable Gate Arrays Dig. Tech. Paper, pp. 113-122, Feb., 2006.
2. M. Miyamura, et al., "Programmable Cell Array Using Rewritable Solid- Electrolyte Switch Integrated in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 228-229, Feb., 2011.
3. T. Naito, et al., "World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS, " IEEE Symposium on VLSI Technology, pp. 219-220, June, 2010.
4. M. Sekikawa, et al., "A Novel SPRAM (SPin-transfer torque RAM)-based Reconfigurable Logic Block for 3D-Stacked reconfigurable Spin Processor," Intl. Electron Device Meeting Tech. Dig., pp. 936-937, Dec., 2008.
5. x RRAM with Sub-uA Programming Current," IEEE Symposium on VLSI Technology, pp. 22-23, June, 2011.
6. Xilinx "Virtex-II Pro Data Sheet," Accessed on Sept., 2011, 〈www.xilinx.com/support/documentation/data-sheets/ds083.pdf〉.